AD9547SLASHPCBZ datasheet(25/104 Pages) AD

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AD9547

Rev. 0 | Page 25 of 104

Program the clock distribution outputs.

The clock distribution parameters reside in the 0x0400 register

address space. They include the following:

•

Output power-down control

•

Output enable (disabled by default)

•

Output synchronization

•

Output mode control

•

Output divider functionality

•

Program the reference inputs.

10. The reference input parameters reside in the 0x0500

•

Reference power-down

•

Reference logic family

•

Reference profile assignment control

•

Phase build-out control

11. Program the reference profiles.

The reference profile parameters reside in the 0x0600 and

0x0700 register address spaces. They include the following:

•

Reference priority

•

Reference period

•

Reference period tolerance

•

Reference validation timer

•

Reference redetect timer

•

Digital loop filter coefficients

•

Reference prescaler (R divider)

•

Feedback dividers (S, U, and V)

•

Phase and frequency lock detector controls

12. Generate reference acquisition.

After the registers are programmed, issue an I/O update using

been programmed up to this point.

If the settings are programmed for manual profile assignment,

the DPLL locks to the first available reference that has the highest

priority. If the settings are programmed for automatic profile

assignment, then write to the reference profile selection register

(Address 0x0A0D) to select the state machines that require starting.

Next, issue an I/O update (Address 0x0005, Bit 0) to start the

selected state machines. Upon completion of the reference

detection sequence, the DPLL locks to the first available

reference with the highest priority.

13. Generate the output clock.

If the registers are programmed for automatic clock distribution

synchronization via DPLL phase or frequency lock, the synthesized

output signal appears at the clock distribution outputs (assuming

that the output is enabled and the DDS output signal has been

routed to the CLKINx input pins). Otherwise, set and then clear

the sync distribution bit (Address 0x0A02, Bit 1) or use a multi-

function pin input (if programmed accordingly) to generate

a clock distribution sync pulse, which causes the synthesized

output signal to appear at the clock distribution outputs.

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