AD9547SLASHPCBZ datasheet(18/104 Pages) AD

18 / 104 page

AD9547

Rev. 0 | Page 18 of 104

TYPICAL PERFORMANCE CHARACTERISTICS

fREF = input reference clock frequency, fO = clock frequency, fSYSCLK = SYSCLK input frequency, fS =internal system clock frequency, LBW =

DPLL loop bandwidth, PLL off = SYSCLK PLL bypassed, PLL on = SYSCLK PLL enabled, ICP = SYSCLK PLL charge pump current, LF =

SYSCLK PLL loop filter. AVDD, AVDD3, and DVDD at nominal supply voltage, fS = 1 GHz, ICP = automatic mode, LF = internal, unless

otherwise noted.

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FREQUENCY OFFSET (Hz)

INTEGRATED RMS JITTER (PHASE NOISE):

5kHz TO 20MHz: 173fs (–75.4dBc)

20kHz TO 80MHz: 315fs (–70.2dBc) (EXTRAPOLATED)

Figure 3. Additive Phase Noise (Output Driver = LVPECL),

fREF = 19.44 MHz, fO = 155.52 MHz,

LBW = 1 kHz, fSYSCLK = 1 GHz, PLL Off

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100M

FREQUENCY OFFSET (Hz)

INTEGRATED RMS JITTER (PHASE NOISE):

5kHz TO 20MHz: 333fs (–69.8dBc)

20kHz TO 80MHz: 430fs (–67.6dBc) (EXTRAPOLATED)

Figure 4. Additive Phase Noise (Output Driver = LVPECL),

fREF = 19.44 MHz, fO = 155.52 MHz,

LBW = 1 kHz, fSYSCLK = 50 MHz (Crystal), PLL On

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–150

–140

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–110

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100

10k

100k

10M

100M

FREQUENCY OFFSET (Hz)

INTEGRATED RMS JITTER (PHASE NOISE):

5kHz TO 20MHz: 103fs (–74.0dBc)

20kHz TO 80MHz: 160fs (–70.1dBc)

Figure 5. Additive Phase Noise (Output Driver = LVPECL),

fREF = 19.44 MHz, fO = 311.04 MHz,

LBW = 1 kHz, fSYSCLK = 1 GHz, PLL Off

–160

–150

–140

–130

–120

–110

–100

–90

–80

–70

100

10k

100k

10M

100M

FREQUENCY OFFSET (Hz)

INTEGRATED RMS JITTER (PHASE NOISE):

5kHz TO 20MHz: 310fs (–64.4dBc)

20kHz TO 80MHz: 330fs (–63.9dBc)

Figure 6. Additive Phase Noise (Output Driver = LVPECL),

fREF = 19.44 MHz, fO = 311.04 MHz,

LBW = 1 kHz, fSYSCLK = 50 MHz (Crystal), PLL On

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AD9547/PCBZ 数据表(PDF) 18 Page - Analog Devices

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