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AD9547/PCBZ 数据表(PDF) 95 Page - Analog Devices |
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AD9547/PCBZ 数据表(HTML) 95 Page - Analog Devices |
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95 / 104 page  AD9547 Rev. 0 | Page 95 of 104 Table 145. Load Address Bit Bit Name Description 0x0E03 [7:2] Unused Unused. 1 Load from EEPROM Download data from the EEPROM. This is an autoclearing bit. 0 Unused Unused. EEPROM STORAGE SEQUENCE (REGISTER 0x0E10 TO REGISTER 0x0E3F) The default settings of Register 0x0E10 to Register 0x0E33 embody a sample scratch pad instruction sequence. The following is a description of the register defaults under the assumption that the controller has been instructed to carry out an EEPROM storage sequence. Table 146. EEPROM Storage Sequence for System Clock Settings Address Bit Bit Name Description 0x0E10 [7:0] System clock The default value of this register is 0x08, which the controller interprets as a data instruction. Its decimal value is 8, which tells the controller to transfer nine bytes of data (8 + 1) beginning at the address specified by the next two bytes. The controller stores 0x08 in the EEPROM and increments the EEPROM address pointer. 0x0E11 [7:0] System clock The default value of these two registers is 0x0100. Note that Register 0x0E11 and Register 0x0E12 are the most significant and least significant bytes of the target address, respectively. Because the previous register contains a data instruction, these two registers define a starting address (in this case, 0x0100). The controller stores 0x0100 in the EEPROM and increments the EEPROM pointer by 2. It then transfers nine bytes from the register map (beginning at Address 0x0100) to the EEPROM and increments the EEPROM address pointer by 10 (nine data bytes and one checksum byte). The nine bytes transferred correspond to the system clock parameters in the register map. 0x0E12 [7:0] 0x0E13 [7:0] I/O update The default value of this register is 0x80, which the controller interprets as an I/O update instruction. The controller stores 0x80 in the EEPROM and increments the EEPROM address pointer. Table 147. EEPROM Storage Sequence for System Clock Calibration Address Bit Bit Name Description 0x0E14 [7:0] SYSCLK calibrate The default value of this register is 0xA0, which the controller interprets as a calibrate instruction. The controller stores 0xA0 in the EEPROM and increments the EEPROM address pointer. Table 148. EEPROM Storage Sequence for General Configuration Settings Address Bit Bit Name Description 0x0E15 [7:0] General The default value of this register is 0x14, which the controller interprets as a data instruction. Its decimal value is 20, which tells the controller to transfer 21 bytes of data (20 + 1) beginning at the address specified by the next two bytes. The controller stores 0x14 in the EEPROM and increments the EEPROM address pointer. 0x0E16 [7:0] General The default value of these two registers is 0x0200. Note that Register 0x0E16 and Register 0x0E17 are the most significant and least significant bytes of the target address, respectively. Because the previous register contains a data instruction, these two registers define a starting address (in this case, 0x0200). The controller stores 0x0200 in the EEPROM and increments the EEPROM pointer by 2. It then transfers 21 bytes from the register map (beginning at Address 0x0200) to the EEPROM and incre- ments the EEPROM address pointer by 22 (21 data bytes and one checksum byte). The 21 bytes transferred correspond to the general configuration parameters in the register map. 0x0E17 [7:0] Table 149. EEPROM Storage Sequence for DPLL Settings Address Bit Bit Name Description 0x0E18 [7:0] DPLL The default value of this register is 0x1B, which the controller interprets as a data instruction. Its decimal value is 27, which tells the controller to transfer 28 bytes of data (27 + 1) beginning at the address specified by the next two bytes. The controller stores 0x1B in the EEPROM and increments the EEPROM address pointer. 0x0E19 [7:0] DPLL The default value of these two registers is 0x0300. Note that Register 0x0E19 and Register 0x0E1A are the most significant and least significant bytes of the target address, respectively. Because the previous register contains a data instruction, these two registers define a starting address (in this case, 0x0300). The controller stores 0x0300 in the EEPROM and increments the EEPROM pointer by 2. It then transfers 28 bytes from the register map (beginning at Address 0x0300) to the EEPROM and increments the EEPROM address pointer by 29 (28 data bytes and one checksum byte). The 28 bytes transferred correspond to the DPLL parameters in the register map. 0x0E1A [7:0] |
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