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AD9547/PCBZ 数据表(PDF) 16 Page - Analog Devices |
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AD9547/PCBZ 数据表(HTML) 16 Page - Analog Devices |
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16 / 104 page  AD9547 Rev. 0 | Page 16 of 104 Pin No. Input/ Output Pin Type Mnemonic Description 20 I Differential input CLKINN Clock Distribution Input. In standard operating mode, this pin is connected to the filtered DACOUTN output. This internally biased input is typically ac-coupled, and, when configured as such, can accept any differential signal with a single- ended swing of at least 400 mV. 21 I Differential input CLKINP Clock Distribution Input. In standard operating mode, this pin is connected to the filtered DACOUTP output. 23 I Power AVDD 1.8 V Analog (Input Receiver) Power Supply. 24 O Current set resistor OUT_RSET Connect an optional 3.12 kΩ resistor from this pin to ground (see the Output Current Control with an External Resistor section). 25, 31 I Power AVDD3 Analog Supply for Output Driver. These pins are normally 3.3 V but can be 1.8 V. Pin 25 powers OUT0. Pin 31 powers OUT1. Apply power to these pins even if the corresponding outputs (OUT0P/OUT0N, OUT1P/OUT1N) are not used (see the Power Supply Partitions section). 26 O LVPECL, LVDS, or CMOS OUT0P Output 0. This output can be configured as LVPECL, LVDS, or single-ended CMOS. LVPECL and LVDS operation require a 3.3 V output driver power supply. CMOS operation can be either 1.8 V or 3.3 V, depending on the output driver power supply. 27 O LVPECL, LVDS, or CMOS OUT0N Complementary Output 0. This output can be configured as LVPECL, LVDS, or single-ended CMOS. 28, 32 I Power AVDD 1.8 V Analog (Output Divider) Power Supply. 29 O LVPECL, LVDS, or CMOS OUT1P Output 1. This output can be configured as LVPECL, LVDS, or single-ended CMOS. LVPECL and LVDS operation require a 3.3 V output driver power supply. CMOS operation can be either 1.8 V or 3.3 V, depending on the output driver power supply. 30 O LVPECL, LVDS, or CMOS OUT1N Complementary Output 1. This output can be configured as LVPECL, LVDS, or single-ended CMOS. 33 I Power AVDD3 3.3 V Analog (System Clock) Power Supply. 34 I SYSCLK_VREG System Clock Loop Filter Voltage Regulator. Connect a 0.1 μF capacitor from this pin to ground. This pin is also the ac ground reference for the integrated external loop filter of the SYSCLK PLL multiplier (see the SYSCLK PLL Multiplier section). 35 O SYSCLK_LF System Clock Multiplier Loop Filter. When using the frequency multiplier to drive the system clock, an external loop filter can be attached to this pin. 36, 39 I Power AVDD 1.8 V Analog (System Clock) Power Supply. 37 I Differential input SYSCLKN Complementary System Clock Input. Complementary signal to SYSCLKP. SYSCLKN contains internal dc biasing and should be ac-coupled with a 0.01 μF capacitor, except when using a crystal. When using a crystal, connect it across SYSCLKP and SYSCLKN. 38 I Differential input SYSCLKP System Clock Input. SYSCLKP contains internal dc biasing and should be ac- coupled with a 0.01 μF capacitor, except when using a crystal. When using a crystal, connect it directly across SYSCLKP and SYSCLKN. Single-ended 1.8 V CMOS is also an option but can introduce a spur if the duty cycle is not 50%. When using SYSCLKP as a single-ended input, connect a 0.01 μF capacitor from SYSCLKN to ground. 40, 41 I TDC_VRB, TDC_VRT Use capacitive decoupling on these pins (see Figure 36). 42 I Power AVDD 1.8 V Analog (Time-to-Digital Converter) Power Supply. 43, 49 I Power AVDD3 3.3 V Analog (Reference Input) Power Supply. 44 I Differential input REFA Reference A Input. This internally biased input is typically ac-coupled and, when configured as such, can accept any differential signal with a single- ended swing of up to 3.3 V. If dc-coupled, input can be LVPECL, CMOS, or LVDS. 45 I Differential input REFAA Complementary Reference A Input. Complementary signal to the input pro- vided on Pin 44. The user can configure this pin as a separate single-ended input. 46, 50 I Power AVDD 1.8 V Analog (Reference Input) Power Supply. |
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