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AD9547/PCBZ 数据表(PDF) 89 Page - Analog Devices |
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AD9547/PCBZ 数据表(HTML) 89 Page - Analog Devices |
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89 / 104 page  AD9547 Rev. 0 | Page 89 of 104 Table 120. Cal/Sync Address Bit Bit Name Description 0x0A02 [7:2] Unused Unused. 1 Sync distribution Setting this bit (default = 0) initiates synchronization of the clock distribution output. When this bit = 1, the clock distribution output stalls. Synchronization occurs on the 1 to 0 transition of this bit. 0 Calibrate SYSCLK Setting this bit (default = 0) initiates an internal calibration of the SYSCLK PLL (assuming it is enabled). The calibration routine automatically selects the proper VCO frequency band and signal amplitude. The internal system clock stalls during the calibration procedure, disabling the device until calibration is complete (a few ms). Register 0x0A03—Reset Functions Table 121. Reset Functions1 Address Bit Bit Name Description 0x0A03 7 Unused Unused. 6 Clear LF Setting this bit (default = 0) clears the digital loop filter (intended as a debug tool). 5 Clear CCI Setting this bit (default = 0) clears the CCI filter (intended as a debug tool). 4 Clear phase accumulator Setting this bit (default = 0) clears DDS phase accumulator (not a recommended action). 3 Reset auto sync Setting this bit (default = 0) resets the automatic synchronization logic (see Register 0x0403). 2 Reset TW history Setting this bit (default = 0) resets the tuning word history logic (part of holdover functionality). 1 Reset all IRQs Setting this bit (default = 0) clears the entire IRQ monitor register (Register 0x0D02 to Register 0x0D09). It is the equivalent of setting all the bits of the IRQ clearing register (Register 0x0A04 to Register 0x0A0B). 0 Reset watchdog Setting this bit (default = 0) resets the watchdog timer (see Register 0x0211 to Register 0x0212). If the timer times out, it simply starts a new timing cycle. If the timer has not yet timed out, it restarts at Time 0 without causing a timeout event. Continuously resetting the watchdog timer at intervals less than its timeout period prevents the watchdog timer from generating a timeout event. 1 All bits in this register are autoclearing. Register 0x0A04 to Register 0x0A0B—IRQ Clearing The IRQ clearing registers are identical in format to the IRQ monitor registers (Address 0x0D02 to Address 0x0D09). When set to Logic 1, an IRQ clearing bit resets the corresponding IRQ monitor bit, thereby canceling the interrupt request for the indicated event. The IRQ clearing register is an autoclearing register. Table 122. IRQ Clearing for SYSCLK Address Bit Bit Name Description 0x0A04 [7:6] Unused Unused. 5 SYSCLK unlocked Clears SYSCLK unlocked IRQ. 4 SYSCLK locked Clears SYSCLK locked IRQ. [3:2] Unused Unused. 1 SYSCLK cal complete Clears SYSCLK calibration complete IRQ. 0 SYSCLK cal started Clears SYSCLK calibration started IRQ. Table 123. IRQ Clearing for Distribution Sync, Watchdog Timer, and EEPROM Address Bit Bit Name Description 0x0A05 [7:4] Unused Unused. 3 Distribution sync Clears distribution sync IRQ. 2 Watchdog timer Clears watchdog timer IRQ. 1 EEPROM fault Clears EEPROM fault IRQ. 0 EEPROM complete Clears EEPROM complete IRQ. |
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