 |
数据搜索系统，热门电子元器件搜索 |
|
|
数据搜索系统，热门电子元器件搜索 |
|
AD9547/PCBZ 数据表(PDF) 97 Page - Analog Devices |
|
|
|||||||||||||||||||||||||||||
AD9547/PCBZ 数据表(HTML) 97 Page - Analog Devices |
|
|
97 / 104 page  AD9547 Rev. 0 | Page 97 of 104 Table 154. EEPROM Storage Sequence for Profile 4 and Profile 5 Settings Address Bit Bit Name Description 0x0E28 [7:0] Profile 4 and Profile 5 The default value of this register is 0x63, which the controller interprets as a data instruction. Its decimal value is 99, which tells the controller to transfer 100 bytes of data (99 + 1) beginning at the address specified by the next two bytes. The controller stores 0x63 in the EEPROM and increments the EEPROM address pointer. 0x0E29 [7:0] Profile 4 and Profile 5 The default value of these two registers is 0x0700. Note that Register 0x0E29 and Register 0x0E2A are the most significant and least significant bytes of the target address, respectively. Because the previous register contains a data instruction, these two registers define a starting address (in this case, 0x0700). The controller stores 0x0700 in the EEPROM and increments the EEPROM pointer by 2. It then transfers 100 bytes from the register map (beginning at Address 0x0700) to the EEPROM and increments the EEPROM address pointer by 101 (100 data bytes and one checksum byte). The 99 bytes transferred correspond to the Profile 4 and Profile 5 parameters in the register map. 0x0E2A [7:0] Table 155. EEPROM Storage Sequence for Profile 6 and Profile 7 Settings Address Bit Bit Name Description 0x0E2B [7:0] Profile 6 and Profile 7 The default value of this register is 0x63, which the controller interprets as a data instruction. Its decimal value is 99, this tells the controller to transfer 100 bytes of data (99 + 1) beginning at the address specified by the next two bytes. The controller stores 0x63 in the EEPROM and increments the EEPROM address pointer. 0x0E2C [7:0] Profile 6 and Profile 7 The default value of these two registers is 0x0780. Note that Register 0x0E2C and Register 0x0E2D are the most significant and least significant bytes of the target address, respectively. Because the previous register contains a data instruction, these two registers define a starting address (in this case, 0x0780). The controller stores 0x0780 in the EEPROM and increments the EEPROM pointer by 2. It then transfers 100 bytes from the register map (beginning at Address 0x0780) to the EEPROM and increments the EEPROM address pointer by 101 (100 data bytes and one checksum byte). The 99 bytes transferred correspond to the Profile 6 and Profile 7 parameters in the register map. 0x0E2D [7:0] 0x0E2E [7:0] I/O update The default value of this register is 0x80, which the controller interprets as an I/O update instruction. The controller stores 0x80 in the EEPROM and increments the EEPROM address pointer. Table 156. EEPROM Storage Sequence for Operational Control Settings Address Bit Bit Name Description 0x0E2F [7:0] Operational controls The default value of this register is 0x10, which the controller interprets as a data instruction. Its decimal value is 16, this tells the controller to transfer 17 bytes of data (16 + 1) beginning at the address specified by the next two bytes. The controller stores 0x10 in the EEPROM and increments the EEPROM address pointer. 0x0E30 [7:0] Operational controls The default value of these two registers is 0x0A00. Note that Register 0x0E30 and Register 0x0E31 are the most significant and least significant bytes of the target address, respectively. Because the previous register contains a data instruction, these two registers define a starting address (in this case, 0x0A00). The controller stores 0x0A00 in the EEPROM and increments the EEPROM pointer by 2. It then transfers 17 bytes from the register map (beginning at Address 0x0A00) to the EEPROM and increments the EEPROM address pointer by 18 (17 data bytes and one checksum byte). The 17 bytes transferred correspond to the operational controls parameters in the register map. 0x0E31 [7:0] 0x0E32 [7:0] I/O update The default value of this register is 0x80, which the controller interprets as an I/O update instruction. The controller stores 0x80 in the EEPROM and increments the EEPROM address pointer. Table 157. EEPROM Storage Sequence for End of Data Address Bit Bit Name Description 0x0E33 [7:0] End of data The default value of this register is 0xFF, which the controller interprets as an end instruction. The controller stores this instruction in the EEPROM, resets the EEPROM address pointer, and enters an idle state. Note that, if this were a pause rather than an end instruction, the controller actions would be the same except that the controller would not reset the EEPROM address pointer. |
|
链接网址 |
| ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 数据表链接 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Chinese ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
