AD9547SLASHPCBZ datasheet(54/104 Pages) AD

54 / 104 page

AD9547

Rev. 0 | Page 54 of 104

I²C SERIAL PORT OPERATION

The I2C interface has the advantage of requiring only two

control pins and is a de facto standard throughout the I2C

industry. However, its disadvantage is programming speed,

which is 400 kbps maximum. The AD9547 I2C port design is

based on the I2C fast mode standard from Philips, so it supports

both the 100 kHz standard mode and the 400 kHz fast mode.

Fast mode imposes a glitch tolerance requirement on the control

signals; that is, the input receivers ignore pulses of less than

50 ns duration.

The AD9547 I2C port consists of a serial data line (SDA) and

a serial clock line (SCL). In an I2C bus system, the AD9547 is

connected to the serial bus (data bus SDA and clock bus SCL)

as a slave device; that is, no clock is generated by the AD9547.

The AD9547 uses direct 16-bit memory addressing instead of

traditional 8-bit memory addressing.

The AD9547 allows for up to seven unique slave devices to occupy

the I2C bus. These are accessed via a 7-bit slave address that is

transmitted as part of an I2C packet. Only the device with a match-

ing slave address responds to subsequent I2C commands. The

device slave address is 1001xxx (the last three bits are determined

by the M0 to M2 pins). The four MSBs (1001) are hardwired,

whereas the three LSBs (xxx, determined by the M0 to M2 pins)

are programmable via the power-up state of the multifunction

pins (see the Initial M0 to M7 Pin Programming section).

I2C Bus Characteristics

A summary of the various I2C protocols appears in Table 34.

Table 34. I2C Bus Abbreviation Definitions

Abbreviation

Definition

Start

Repeated start

Stop

Acknowledge

No acknowledge

Write

Read

The transfer of data appears graphically in Figure 57. One clo

pulse is generated for each data bit transferred. The data on the

SDA line must be stable during the

high period of the clock.

The high or low state of the data line can change only when the

clock signal on the SCL line is low.

DATA

SDA

LINE

BLE;

CHANGE

OF DATA

STA

DATA VALID

ALLOWED

SCL

n on the

SDA line while SCL is high. The stop condition is always

generated by the master to terminate data transfer.

Figure 57. Valid Bit Transfer

Start/stop functionality appears graphically in Figure 58. The

start condition is characterized by a high-to-low transition o

the SDA line while SCL is high. The start condition is always

generated by the master to initialize data transfer. The stop

condition is characterized by a low-to-high transitio

SDA

START CONDITION

STOP CONDITION

SCL

Figure 58. Start and Stop Condition

t the

Every byte on the SDA line must be eight bits long. Each byte

must be followed by an acknowledge bit. Bytes are sent MSB first.

The acknowledge bit (A) is the ninth bit attached to any 8-bit

data byte. An acknowledge bit is always generated by the

receiving device (receiver) to inform the transmitter tha

byte has been received. It is done by pulling the SDA line low

during the ninth clock pulse after each 8-bit data byte.

The no acknowledge bit (A) is the ninth bit attached to any 8-bit

data byte. A no acknowledge bit is always generated by the

receiving device (receiver) to inform the transmitter that the

byte has not been received. It is done by leaving the SDA line

high during the ninth clock pulse after each 8-bit data byte.

3 TO 7

SDA

SCL

MSB

ACK FROM

SLAVE RECEIVER

ACK FROM

SLAVE RECEIVER

Figure 59. Acknowledge Bit

AD9547/PCBZ 数据表(PDF) 54 Page - Analog Devices

AD9547/PCBZ 数据表(HTML) 54 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载