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AD9547/PCBZ 数据表(PDF) 93 Page - Analog Devices |
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AD9547/PCBZ 数据表(HTML) 93 Page - Analog Devices |
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93 / 104 page  AD9547 Rev. 0 | Page 93 of 104 Table 137. IRQ Monitor for History Update, Frequency Limit, and Phase Slew Limit Address Bit Bit Name Description 0x0D05 [7:5] Unused Unused. 4 History updated Indicates the occurrence of a tuning word history update. 3 Frequency unclamped Indicates a frequency limiter state transition from clamped to unclamped. 2 Frequency clamped Indicates a frequency limiter state transition from unclamped to clamped. 1 Phase slew unlimited Indicates a phase slew limiter state transition from slew limiting to not slew limiting. 0 Phase slew limited Indicates a phase slew limiter state transition from not slew limiting to slew limiting. Table 138. IRQ Monitor for Reference Inputs Address Bit Bit Name Description 0x0D06 7 Ref AA new profile Indicates that Ref AA has switched to a new profile. 6 Ref AA validated Indicates that Ref AA has been validated. 5 Ref AA fault cleared Indicates that Ref AA has been cleared of a previous fault. 4 Ref AA fault Indicates that Ref AA has been faulted. 3 Ref A new profile Indicates that Ref A has switched to a new profile. 2 Ref A validated Indicates that Ref A has been validated. 1 Ref A fault cleared Indicates that Ref A has been cleared of a previous fault. 0 Ref A fault Indicates that Ref A has been faulted. 0x0D07 7 Ref BB new profile Indicates that Ref BB has switched to a new profile. 6 Ref BB validated Indicates that Ref BB has been validated. 5 Ref BB fault cleared Indicates that Ref BB has been cleared of a previous fault. 4 Ref BB fault Indicates that Ref BB has been faulted. 3 Ref B new profile Indicates that Ref B has switched to a new profile. 2 Ref B validated Indicates that Ref B has been validated. 1 Ref B fault cleared Indicates that Ref B has been cleared of a previous fault. 0 Ref B fault Indicates that Ref B has been faulted. 0x0D08 [7:0] Unused Unused. 0x0D09 [7:0] Table 139. DPLL Status Address Bit Bit Name Description 0x0D0A 7 Offset slew limiting The current closed-loop phase offset is rate limited. 6 Phase build-out A phase build-out transition was made to the currently active reference. 5 Frequency lock The DPLL has achieved frequency lock. 4 Phase lock The DPLL has achieved phase lock. 3 Loop switching The DPLL is in the process of a reference switchover. 2 Holdover The DPLL is in holdover mode. 1 Active The DPLL is active (that is, operating in a closed-loop condition). 0 Free running The DPLL is free running (that is, operating in an open-loop condition). 0x0D0B 7 Frequency clamped The upper or lower frequency tuning word clamp is in effect. 6 History available There is sufficient tuning word history available for holdover operation. [5:3] Active reference priority Priority value of the currently active reference. 000 = highest priority. 111 = lowest priority. 2 Unused Unused. [1:0] Active reference Index of the currently active reference. 00 = Reference A. 01 = Reference AA. 10 = Reference B. 11 = Reference BB. |
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