AD9547SLASHPCBZ datasheet(68/104 Pages) AD

68 / 104 page

AD9547

Rev. 0 | Page 68 of 104

SYSTEM CLOCK (SYSCLK) (REGISTER 0x0100 TO REGISTER 0x0108)

Table 43. Charge Pump and Lock Detect Control

Address

Bit

Bit Name

Description

0x0100

External loop filter enable

Enables use of an external SYSCLK PLL loop filter.

0 (default) = internal loop filter.

1 = external loop filter.

Charge pump mode

Charge pump current control.

0 (default) = automatic.

1 = manual.

[5:3]

Charge pump current

Selects charge pump current when Bit 6 = 1.

000 = 125 μA.

001 = 250 μA.

010 = 375 μA.

011 (default) = 500 μA.

100 = 625 μA.

101 = 750 μA.

110 = 875 μA.

111 = 1000 μA.

Lock detect timer disable

Enable the SYSCLK PLL lock detect timer.

0 (default) = enable.

1 = disable.

[1:0]

Lock detect timer

Select lock detect timer depth.

00 (default) = 128.

01 = 256.

10 = 512.

11 = 1024.

Table 44. N Divider

Address

Bit

Bit Name

Description

0x0101

[7:0]

N divider

System clock PLL feedback divider value: 6 ≤ N ≤ 255 (default = 0x28 = 40).

Table 45. System Clock Input Options

Address

Bit

Bit Name

Description

0x0102

Unused

Unused.

M divider reset

Reset the M divider.

0 = normal operation.

1 (default) = reset.

When not using the M divider, program this bit to Logic 1.

[5:4]

M divider

System clock input divider.

00 (default) = 1.

01 = 2.

10 = 4.

11 = 8.

2× frequency multiplier

enable

Enable the 2× frequency multiplier.

0 (default) = disable.

1 = enable.

PLL enable

Enable the SYSCLK PLL.

0 = disable.

1 (default) = enable.

[1:0]

SYSCLK source

Input mode select for SYSCLKx pins.

00 = crystal resonator.

01 (default) = low frequency clock source.

10 = high frequency (direct) clock source.

11 = input receiver power-down.

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