AD9547SLASHPCBZ datasheet(40/104 Pages) AD

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AD9547

Rev. 0 | Page 40 of 104

Super-Nyquist operation requires a band-pass filter at the DAC

output instead of the usual low-pass reconstruction filter. Super-

Nyquist operation is viable as long as the image frequency does

not exceed the 800 MHz input range of the receiver. Furthermore,

to provide acceptable jitter performance, which is a consideration

for image signals with low amplitude, the signal at the CLKINx

inputs must meet the minimum slew rate requirements.

Clock Dividers

The output clock distribution dividers are referred to as Q0 and Q1,

corresponding to the OUT0 and OUT1 output channels, respec-

tively. Each divider is programmable with 30 bits of division depth.

The actual divide ratio is one more than the programmed register

value; therefore, a register value of 3, for example, results in a

divide ratio of 4. Thus, each divider offers a range of divide ratios

from 1 to 230 (1 to 1,073,741,824).

With an even divide ratio, the output signal always exhibits a

50% duty cycle. When the clock divider is bypassed (a divide

ratio of 1), the output duty cycle is the same as the input duty

cycle. Odd output divide ratios (excluding 1) exhibit automatic

duty cycle correction given by

Cycle

Duty

Output

−

where:

N (which must be an odd number) is the divide ratio.

X is the normalized fraction of the high portion of the input period

(that is, 0 < X < 1).

For example, if N = 5 and the input duty cycle is 20% (X = 0.2),

then the output duty cycle is 44%. Note that, when the user

programs an output as noninverting, then the device adjusts the

falling edge timing to accomplish the duty cycle cor-rection.

Conversely, the device adjusts the rising edge timing for an

inverted output.

Output Power-Down

Each output channel offers independent control of power-down

functionality via the distribution settings register (Address 0x0400).

Each output channel has a dedicated power-down bit for powering

down the output driver. However, if both channels are powered

down, the entire distribution output enters a deep sleep mode.

Even though each channel has a channel power-down control

signal, it may sometimes be desirable to power down an output

driver while maintaining the divider’s synchronization with the

other channel dividers. This is accomplished by either of the

following methods:

•

In CMOS mode, use the divider output enable control bit

to stall an output. This provides power savings while main-

taining dc drive at the output.

•

In LVDS/LVPECL mode, place the output in tristate mode

(this works in CMOS mode as well).

Output Enable

Each output channel offers independent control of enable/

disable functionality using the distribution enable register

(Address 0x0401). The distribution outputs use synchronization

logic to control enable/disable activity to avoid the production

of runt pulses and to ensure that outputs with the same divide

ratios become active/inactive in unison.

Output Mode

The user has independent control of the operating mode of each of

the two output channels via the distribution channel modes register

(Address 0x0404 and Address 0x0405). The operating mode

control includes

•

Logic family and pin functionality

•

Output drive strength

•

Output polarity

The three LSBs of both distribution channel mode registers com-

prise the mode bits. The mode value selects the desired logic

family and pin functionality of an output channel, as listed in

Table 23.

Table 23. Output Channel Logic Family and Pin Functionality

Mode Bits [2:0]

Logic Family and Pin Functionality

000

CMOS (both pins)

001

CMOS (positive pin), tristate (negative pin)

010

Tristate (positive pin), CMOS (negative pin)

011

Tristate (both pins)

100

LVDS

101

LVPECL

110

Unused

111

Unused

Regardless of the selected logic family, each is capable of dc

operation. However, the upper frequency is limited by the load

conditions, drive strength, and impedance matching inherent in

each logic family. Practical limitations set the maximum CMOS

frequency to approximately 250 MHz, whereas LVPECL and

LVDS are capable of 725 MHz.

In addition to the three mode bits, both distribution channel

mode registers include the following control bits:

•

Polarity invert

•

CMOS phase invert

•

Drive strength

The polarity invert bit enables the user to choose between normal

polarity and inverted polarity. Normal polarity is the default

state. Inverted polarity reverses the representation of Logic 0

and Logic 1 regardless of the logic family.

The CMOS phase invert bit applies only when the mode bits select

the CMOS logic family. In CMOS mode, both output pins of the

channel have a dedicated CMOS driver. By default, both drivers

deliver identical signals. However, setting the CMOS phase invert

bit causes the signal on an OUTxN pin to be the opposite of the

signal appearing on the OUTxP pin.

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