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AD9547/PCBZ 数据表(PDF) 11 Page - Analog Devices

部件名 AD9547/PCBZ
功能描述  Dual/Quad Input Network Clock Generator/Synchronizer
PDF  104 Pages
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

AD9547/PCBZ 数据表(HTML) 11 Page - Analog Devices

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AD9547
Rev. 0 | Page 11 of 104
SERIAL PORT SPECIFICATIONS—SPI MODE
Table 17.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
CS
Internal 30 kΩ pull-up resistor
Input Logic 1 Voltage
2.0
V
Input Logic 0 Voltage
0.8
V
Input Logic 1 Current
30
μA
Input Logic 0 Current
110
μA
Input Capacitance
2
pF
SCLK
Internal 30 kΩ pull-down resistor
Input Logic 1 Voltage
2.0
V
Input Logic 0 Voltage
0.8
V
Input Logic 1 Current
1
μA
Input Logic 0 Current
1
μA
Input Capacitance
2
pF
SDIO
As an Input
Input Logic 1 Voltage
2.0
V
Input Logic 0 Voltage
0.8
V
Input Logic 1 Current
1
μA
Input Logic 0 Current
1
μA
Input Capacitance
2
pF
As an Output
Output Logic 1 Voltage
2.7
V
1 mA load current
Output Logic 0 Voltage
0.4
V
1 mA load current
SDO
Output Logic 1 Voltage
2.7
V
1 mA load current
Output Logic 0 Voltage
0.4
V
1 mA load current
TIMING
SCLK
Clock Rate, 1/tCLK
40
MHz
Pulse Width High, tHIGH
8
ns
Pulse Width Low, tLOW
12
ns
SDIO to SCLK Setup, tDS
3
ns
SCLK to SDIO Hold, tDH
0
ns
SCLK to Valid SDIO and SDO, tDV
14
ns
CS to SCLK Setup, tS
10
ns
CS to SCLK Hold, tC
0
ns
CS Minimum Pulse Width High
6
ns



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