AD9547SLASHPCBZ datasheet(51/104 Pages) AD

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AD9547

Rev. 0 | Page 51 of 104

SPI Mode Operation

The SPI port supports both 3-wire (bidirectional) and 4-wire

(unidirectional) hardware configurations and both MSB-first

and LSB-first data formats. Both the hardware configuration

and data format features are programmable. By default, the

AD9547 uses the bidirectional MSB-first mode. The bidirectional

mode is the default mode so that the user can still write to the

device to switch to unidirectional mode, if it is wired for

unidirectional operation.

Assertion (active low) of the CS pin initiates a write or read

operation to the AD9547 SPI port. For data transfers of three

bytes or fewer (excluding the instruction word), the device

supports the CS stalled high mode (see

). In this mode,

the

Table 30

CS pin can be temporarily deasserted on any byte boundary,

allowing time for the system controller to process the next byte.

CS can be deasserted only on byte boundaries, however. This

applies to both the instruction and data portions of the transfer.

Table 30. Byte Transfer Count

Bytes to Transfer

Streaming mode

During stall high periods, the serial control port state machine

enters a wait state until all data is sent. If the system controller

decides to abort a transfer midstream, the state machine must be

reset either by completing the transfer or by asserting the CS

pin for at least one complete SCLK cycle (but less than eight

SCLK cycles). Deasserting the CS pin on a nonbyte boundary

terminates the serial transfer and flushes the buffer.

In streaming mode (see Table 30), any number of data bytes can

be transferred in a continuous stream. The register address is

automatically incremented or decremented. CS must be deas-

serted at the end of the last byte transferred, thereby ending the

stream mode.

Communication Cycle—Instruction Plus Data

The SPI protocol consists of a two-part communication cycle.

The first part is a 16-bit instruction word that is coincident with

the first 16 SCLK rising edges and a payload. The instruction word

provides the AD9547 serial control port with information regard-

ing the payload. The instruction word includes the R/W bit that

indicates the direction of the payload transfer (that is, a read or

write operation). The instruction word also indicates the number

of bytes in the payload and the starting register address of the

first payload byte.

Write

If the instruction word indicates a write operation, the payload

is written into the serial control port buffer of the AD9547. Data

bits are registered on the rising edge of SCLK. The length of the

transfer (1, 2, or 3 bytes or streaming mode) depends on the W0

and W1 bits (see Table 30) in the instruction byte. When not

streaming, CS can be deasserted after each sequence of eight

bits to stall the bus (except after the last byte, where it ends the

cycle). When the bus is stalled, the serial transfer resumes when

CS is asserted. Deasserting the CS pin on a nonbyte boundary

resets the serial control port. Reserved or blank registers are not

skipped over automatically during a write sequence. Therefore,

the user must know what bit pattern to write to the reserved

registers to preserve proper operation of the part. Generally, it

does not matter what data is written to blank registers, but it is

customary to write 0s.

Most of the serial port registers are buffered. Refer to the

Buffered/Active Registers section for details on the difference

between buffered and active registers. Therefore, data written

into buffered registers does not immediately take effect. An addi-

tional operation is needed to transfer buffered serial control port

contents to the registers that actually control the device. This is

accomplished with an I/O update operation that is performed

in one of two ways: by writing a Logic 1 to Register 0x0005, Bit 0

(this bit is self-clearing) or by using an external signal via an

appropriately programmed multifunction pin. The user can

change as many register bits as desired before executing an I/O

update. The I/O update operation transfers the buffer register

contents to their active register counterparts.

Read

The AD9547 supports the long instruction mode only. If the

instruction word indicates a read operation, the next N × 8

SCLK cycles clock out the data from the address specified in the

instruction word. N is the number of data bytes read and depends

on the W0 and W1 bits of the instruction word. The readback

data is valid on the falling edge of SCLK. Blank registers are not

skipped over during readback.

A readback operation takes data from either the serial control

port buffer registers or the active registers, as determined by

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