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AD9547/PCBZ 数据表(PDF) 12 Page - Analog Devices |
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AD9547/PCBZ 数据表(HTML) 12 Page - Analog Devices |
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12 / 104 page  AD9547 Rev. 0 | Page 12 of 104 SERIAL PORT SPECIFICATIONS—I2C MODE Table 18. Parameter Min Typ Max Unit Test Conditions/Comments SDA (AS INPUT), SCL No internal pull-up/pull-down resistor Input Logic 1 Voltage 0.7 × DVDD3 V Input Logic 0 Voltage 0.3 × DVDD3 V Input Current −10 +10 μA For VIN = 10% to 90% of DVDD3 Hysteresis of Schmitt Trigger Inputs 0.015 × DVDD3 V Pulse Width of Spikes That Must Be Suppressed by the Input Filter, tSP 50 ns SDA (AS OUTPUT) Output Logic 0 Voltage 0.4 V IO = 3 mA Output Fall Time from VIHmin to VILmax 20 + 0.1 Cb1 250 ns 10 pF ≤ Cb ≤ 400 pF TIMING SCL Clock Rate 400 kHz Bus Free Time Between a Stop and Start Condition, tBUF 1.3 μs Repeated Start Condition Setup Time, tSU;STA 0.6 μs Repeated Hold Time Start Condition, tHD;STA 0.6 μs After this period, the first clock pulse is generated Stop Condition Setup Time, tSU;STO 0.6 μs Low Period of the SCL Clock, tLOW 1.3 μs High Period of the SCL Clock, tHIGH 0.6 μs SCL/SDA Rise Time, tR 20 + 0.1 Cb1 300 ns SCL/SDA Fall Time, tF 20 + 0.1 Cb1 300 ns Data Setup Time, tSU;DAT 100 ns Data Hold Time, tHD;DAT 100 ns Capacitive Load for Each Bus Line, Cb1 400 pF 1 Cb is the capacitance (pF) of a single bus line. |
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