AD9547SLASHPCBZ datasheet(49/104 Pages) AD

49 / 104 page

AD9547

Rev. 0 | Page 49 of 104

If the condition is not tagged, the controller skips instructions

until it encounters a condition instruction that decodes as a

tagged condition. Note that the condition tag board allows

for multiple conditions to be tagged at any given moment.

This conditional processing mechanism enables the user to

have one download instruction sequence with many possible

outcomes, depending on the value of the condition and the

order in which the controller encounters the condition

instructions.

Table 28 lists a sample EEPROM download instruction

sequence. It illustrates the use of condition instructions

and how they alter the download sequence. The table

begins with the assumption that no conditions are in effect.

That is, the most recently executed condition instruction is

0xB0, or no conditional instructions have been processed.

Table 28. EEPROM Conditional Processing Example

Instruction

Action

0x08

Transfer the system clock register contents

regardless of the current condition

0x01

0x00

0xB1

Tag Condition 1

0x19

Transfer the clock distribution register

contents only if condition = 1

0x04

0x00

0xB2

Tag Condition 2

0xB3

Tag Condition 3

0x07

Transfer the reference input register contents

only if condition = 1, 2, or 3

0x05

0x00

0x0A

Calibrate the system clock only if condition =

1, 2, or 3

0xB0

Clear the condition tag board

0x80

Execute an I/O update, regardless of the value

of the condition

0x0A

Calibrate the system clock, regardless of the

value of the condition

Storing Multiple Device Setups in EEPROM

Conditional processing makes it possible to create a number

of different device setups, store them in EEPROM, and

download a specific setup on demand. To do so, first pro-

gram the device control registers for a specific setup. Then,

store an upload sequence in the EEPROM scratch pad with

the following general form:

Condition instruction (0xB1 to 0xCF) to identify the

setup with a specific condition (1 to 31)

Data instructions (to save the register contents) along

with any required calibrate and/or I/O update

instructions

Pause instruction (0xFE)

With the upload sequence written to the scratch pad, perform

an EEPROM upload (Register 0x0E02, Bit 0).

Now reprogram the device control registers for the next desired

setup. Then store a new upload sequence in the EEPROM scratch

pad with the following general form:

Condition Instruction 0xB0

The next desired condition instruction (0xB1 to 0xCF, but

different from the one used during the previous upload to

identify a new setup)

Data instructions (to save the register contents) along with

any required calibrate and/or I/O update instructions

Pause instruction (FE)

With the upload sequence written to the scratch pad, perform

an EEPROM upload (Register 0x0E02, Bit 0).

Repeat the process of programming the device control registers

for a new setup, storing a new upload sequence in the EEPROM

scratch pad (Step 1 through Step 4) and executing an EEPROM

upload (Register 0x0E02, Bit 0) until all of the desired setups are

uploaded to the EEPROM.

Note that, on the final upload sequence stored in the scratch pad,

the pause instruction (FE) must be replaced with an end instruc-

tion (FF).

To download a specific setup on demand, first store the condition

associated with the desired setup in Register 0x0E01, Bits[4:0].

Then perform an EEPROM download (Register 0x0E03, Bit 1).

Alternatively, to download a specific setup at power-up, apply

the required logic levels necessary to encode the desired condition

on the M3 to M7 multifunction pins. Then power up the device,

and an automatic EEPROM download occurs. The condition

(as established by the M3 to M7 multifunction pins) guides the

download sequence and results in a specific setup.

Keep in mind that the number of setups that can be stored in the

EEPROM is limited. The EEPROM can hold a total of 2048 bytes.

Each nondata instruction requires one byte of storage. Each data

instruction, however, requires N + 4 bytes of storage, where N

is the number of transferred register bytes. The other four bytes

include the data instruction itself (one byte), the target address

(two bytes), and the checksum calculated by the EEPROM con-

troller during the upload sequence (one byte).

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