AD9547SLASHPCBZ datasheet(39/104 Pages) AD

39 / 104 page

AD9547

Rev. 0 | Page 39 of 104

To determine the external loop filter components, the user decides

on the desired open loop bandwidth (fOL) and phase margin (φ).

These parameters allow calculation of the loop filter components,

as follows:

()⎟

⎟

⎠

⎞

⎜⎜

⎝

⎛

sin

VCO

C1 =

)

(

)

tan(

VCO

C2 =

⎟⎟

⎠

⎞

⎜⎜

⎝

⎛

−

)

cos(

)

sin(

)

(

VCO

where:

KVCO = 7 × 107 V/ns (typical).

ICP is the programmed charge pump current (amperes).

N is the programmed feedback divider value.

fOL is the desired open-loop bandwidth (Hz).

Φ is the desired phase margin (radians).

For example, assuming that N = 40, ICP = 0.5 mA, fOL = 400 kHz,

and Φ = 50°, then the loop filter calculations yield R1 = 3.31 kΩ,

C1 = 330 pF, and C2 = 50.4 pF.

System Clock Stability Timer

The system clock stability timer, located in Register 0x0106 to

seconds (ms). If the programmed timer value is 0, the timer

immediately indicates that it has timed out. If the programmed

timer value is nonzero and the SYSCLK PLL is enabled, the timer

starts timing when the SYSCLK PLL lock detector indicates lock

and times out after the prescribed period. However, when the user

disables the SYSCLK PLL, the timer ignores the SYSCLK PLL

lock detector and starts timing the instant that the SYSCLK PLL

is disabled. The user can monitor the status of the stability timer

at Register 0x0D01, Bit 4, via the multifunction pins or via the IRQ

pin.

Note that the system clock stability timer must be programmed

before the SYSCLK PLL is either activated or disabled.

SYSCLK PLL Calibration

When using the SYSCLK PLL, it is necessary to calibrate the

LC-VCO to ensure that the PLL can remain locked to the system

clock input signal. Assuming the presence of either an external

SYSCLK input signal or a crystal resonator, the calibration process

executes after the user sets and then clears the calibrate system

clock bit in the cal/sync register (Register 0x0A02, Bit 0). During

the calibration process, the device calibrates the VCO amplitude

and frequency. The status of the system clock calibration process

is user accessible via the system clock status register (Register

0x0D01, Bit 1). It is also available via the IRQ monitor register

(Bit 1 of Register 0x0D02), provided that the status bit is enabled

via the IRQ mask register (Register 0x0209 and Register 0x0210).

When the calibration sequence is complete, the SYSCLK PLL

eventually attains a lock condition, at which point the system

clock stability timer begins its countdown sequence. Expiration

of the timer indicates that the SYSCLK PLL is stable, which is

reflected in the system clock status register (Register 0x0D01, Bit 4).

Note that the monitors/detectors associated with the input

references (REF A/REF AA and REF B/REF BB) are internally

disabled until the SYSCLK PLL indicates that it is stable.

CLOCK DISTRIBUTION

The clock distribution block of the AD9547 provides an integrated

solution for generating multiple clock outputs based on frequency

dividing the DPLL output. The distribution output consists of

two channels (OUT0 and OUT1). Each channel has a dedicated

divider and output driver section, as shown in Figure 45.

SYNC

CONTROL

ENABLEn/MODEn

SYNC SOURCE

CLKINP

OUT1P

OUT1N

OUT1

OUT0

CLKINN

OUT_RSET

OUT0P

OUT0N

Figure 45. Clock Distribution

Clock Input (CLKINx)

The clock input handles input signals from a variety of logic

families (assuming proper terminations and sufficient voltage

swing). It also handles sine wave input signals such as those

delivered by the DAC reconstruction filter. Its default operating

frequency range is 62.5 MHz to 500 MHz.

Super-Nyquist Operation

Typically, the maximum usable frequency at the DAC output is

about 45% of the system clock frequency. However, because it is

a sampled DAC, its output spectrum contains Nyquist images.

Of particular interest are the images appearing in the first Nyquist

zone (50% to 100% of the system clock frequency). Super-Nyquist

operation takes advantage of these higher frequencies, but this

implies that the CLKINx input operates in excess of 500 MHz,

which is outside its default operating limits.

The CLKINx receiver actually consists of two separate receivers:

the default receiver and an optional high frequency receiver,

which handles input signals up to 800 MHz. To select the high

frequency receiver, write a Logic 1 to Register 0x0400, Bit4.

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