AD9547SLASHPCBZ datasheet(45/104 Pages) AD

45 / 104 page

AD9547

Rev. 0 | Page 45 of 104

At power-up, the multifunction pins can be used to force the device

into certain configurations as defined in the Initial M0 to M7 Pin

Programming section. This functionality, however, is valid only

during power-up or following a reset, after which the pins can

be reconfigured via the serial programming port or via the

EEPROM.

IRQ PIN

The AD9547 has a dedicated interrupt request (IRQ) pin. The

IRQ pin output mode register (Register 0x0208, Bits[1:0]) controls

how the IRQ pin asserts an interrupt based on the value of the

two bits, as shown in Table 26.

Table 26. IRQ Pin Control—Register 0x0208, Bits[1:0]

Setting

Description

The IRQ pin is high impedance when deasserted and

active low when asserted and requires an external

pull-up resistor (this is the default operating mode).

The IRQ pin is high impedance when deasserted and

active high when asserted and requires an external

pull-down resistor.

The IRQ pin is Logic 0 when deasserted and Logic 1

when asserted.

The IRQ pin is Logic 1 when deasserted and Logic 0

when asserted.

The AD9547 asserts the IRQ pin when any of the bits in the IRQ

monitor registers (Address 0x0D02 to Address 0x0D09) are

Logic 1. Each bit in these registers is associated with an internal

function that is capable of producing an interrupt. Furthermore,

each bit of the IRQ monitor register is the result of a logical AND

of the associated internal interrupt signal and the corresponding

bit in the IRQ mask register (Address 0x0209 to Address 0x0210).

That is, the bits in the IRQ mask register have a one-to-one cor-

respondence with the bits in the IRQ monitor register. When an

internal function produces an interrupt signal and the associated

IRQ mask bit is set, the corresponding bit in the IRQ monitor

The user should be aware that clearing a bit in the IRQ mask

interrupt signal. It does not clear the corresponding bit in the

IRQ monitor register.

The IRQ pin is the result of a logical OR of all the IRQ monitor

the IRQ monitor register bits are Logic 1. Note that it is possible

to have multiple bits set in the IRQ monitor register. Therefore,

when the AD9547 asserts the IRQ pin, it may indicate an interrupt

from several different internal functions. The IRQ monitor register

provides the user with a means to interrogate the AD9547 to

determine which internal function(s) produced the interrupt.

Typically, when the AD9547 asserts the IRQ pin, the user inter-

rogates the IRQ monitor register to identify the source of the

interrupt request. After servicing an indicated interrupt, the user

should clear the associated IRQ monitor register bit via the IRQ

clearing registers (Address 0x0A04 to Address 0x0A0B). The bits

in the IRQ clearing register have a one-to-one correspondence

with the bits in the IRQ monitor register. Note that the IRQ

clearing register is autoclearing. The IRQ pin remains asserted

until the user clears all of the bits in the IRQ monitor register

that indicate an interrupt.

It is also possible to collectively clear all of the IRQ monitor

bit. Setting this bit results in deassertion of the IRQ pin. Alter-

natively, the user can program any of the multifunction pins to

clear all IRQs. This allows the user to clear all IRQs by means of

a hardware pin rather than by a serial I/O port operation.

WATCHDOG TIMER

The watchdog timer is a general-purpose, programmable timer.

To set its timeout period, the user writes to the 16-bit watchdog

timer register (Address 0x0211 and Address 0x0212). A value of

zero in this register disables the timer. A nonzero value sets the

timeout period in units of milliseconds (ms), giving the watchdog

timer a range of 1 ms to 65,535 ms. The relative accuracy of the

timer is approximately 0.1% with an uncertainty of 0.5 ms.

If enabled, the timer runs continuously and generates a timeout

event whenever the timeout period expires. The user has access

to the watchdog timer status via the IRQ mechanism and the

multifunction pins (M0 to M7). In the case of the multifunction

pins, the timeout event of the watchdog timer is a pulse that

lasts 32 system clock periods.

There are two ways to reset the watchdog timer (thereby pre-

venting it from causing a timeout event). The first is by writing

a Logic 1 to the autoclearing reset watchdog bit in the reset

functions register (Register 0x0A03, Bit 0). Alternatively, the

user can program any of the multifunction pins to reset the

watchdog timer. This allows the user to reset the timer by means

of a hardware pin rather than by a serial I/O port operation.

AD9547/PCBZ 数据表(PDF) 45 Page - Analog Devices

AD9547/PCBZ 数据表(HTML) 45 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载