AD9547SLASHPCBZ datasheet(24/104 Pages) AD

24 / 104 page

AD9547

Rev. 0 | Page 24 of 104

GETTING STARTED

POWER-ON RESET

The AD9547 monitors the voltage on the power supplies at power-

up. When DVDD3 is greater than 2.35 V ± 0.1 V and DVDD

(Pin 1, Pin 6, Pin 8, Pin 53, Pin 59, and Pin 64) is greater than

1.4 V ± 0.05 V, the device generates a 75 ns reset pulse. The

power-up reset pulse is internal and independent of the RESET

pin. This internal power-up reset sequence eliminates the need for

the user to provide external power supply sequencing. Within 45 ns

after the leading edge of the internal reset pulse, the M0 to M7

multifunction pins function as high impedance digital inputs

and continue to do so until programmed otherwise.

INITIAL M0 TO M7 PIN PROGRAMMING

During a device reset (either via the power-up reset pulse or the

RESET pin), the multifunction pins (M0 to M7) function as

high impedance inputs, but upon removal of the reset condition,

level-sensitive latches capture the logic pattern present on the

multifunction pins. The AD9547 requires that the user supply

the desired logic state to the M0 to M7 pins by means of pull-up

and/or pull-down resistors (nominally 10 kΩ to 30 kΩ).

The initial state of the M0 to M7 pins following a reset is referred

to as FncInit, Bits[7:0]. Bits[7:0] of FncInit map directly to the

logic states of M[7:0], respectively. The three LSBs of FncInit

(FncInit, Bits[2:0]) determine whether the serial port interface

functions according to the SPI or the I2C protocol. Specifically,

FncInit, Bits[2:0] = 000 selects the SPI interface. Any other value

selects the I2C port, with the three LSBs of the I2C bus address

set to the value of FncInit, Bits[2:0].

The five MSBs of FncInit (FncInit, Bits[7:3]) determine the opera-

tion of the EEPROM loader. On the falling edge of RESET, if

FncInit, Bits[7:3] = 00000, then the EEPROM contents are not

transferred to the control registers and the device registers assume

their default values. However, if FncInit, Bits[7:3] ≠ 00000, then

the EEPROM controller transfers the contents of the EEPROM

to the control registers with CONDITION = FncInit, Bits[7:3]

(see the EEPROM section).

DEVICE REGISTER PROGRAMMING

The initial state of the M0 to M7 pins establishes the serial I/O

port protocol (SPI or I2C). Using the appropriate serial port pro-

tocol, and assuming that an EEPROM download is not used,

program the device according to the recommended sequence

that follows.

Program the system clock functionality.

The system clock parameters reside in the 0x100 register

address space. They include the following:

•

System clock PLL controls

•

System clock period

•

System clock stability timer

It is essential to program the system clock period because many

of the AD9547 subsystems rely on this value. It is highly recom-

mended that the system clock stability timer be programmed, as

well. This is especially important when using the system clock PLL

but also applies if using an external system clock source, especially

if the external source is not expected to be completely stable when

power is applied to the AD9547.

Initialize the system clock.

After the system clock functionality is programmed, issue an I/O

update using Register 0x0005, Bit 0 to invoke the system clock

settings.

Calibrate the system clock (only if using SYSCLK PLL).

Set the calibrate system clock bit in the cal/sync register

(Address 0x0A02, Bit 0) and issue an I/O update. Then clear the

calibrate system clock bit and issue another I/O update. This

action allows time for the calibration to proceed while pro-

gramming the remaining device registers.

Program the multifunction pins (optional).

This step is required only if the user intends to use any of the

multifunction pins for status or control. The multifunction pin

parameters reside in the 0x0200 register address space. The

default configuration of the multifunction pins is as undesignated

high impedance input pins.

Program the IRQ functionality (optional).

This step is required only if the user intends to use the IRQ feature.

IRQ control resides in the 0x0200 register address space. It includes

the following:

•

IRQ pin mode control

•

IRQ mask

The IRQ mask default values prevent interrupts from being

generated. The IRQ pin mode default is open-drain NMOS.

Program the watchdog timer (optional).

This step is required only if the user intends to use the watchdog

timer. Watchdog timer control resides in the 0x0200 register

address space. The watchdog timer is disabled by default.

Program the DAC full-scale current (optional).

This step is required only if the user intends to use a full-scale

current setting other than the default value. DAC full-scale

current control resides in the 0x0200 register address space.

Program the digital phase-locked loop (DPLL).

The DPLL parameters reside in the 0x0300 register address

space. They include the following:

•

Free-run frequency (DDS frequency tuning word)

•

DDS phase offset

•

DPLL pull-in range limits

•

DPLL closed-loop phase offset

•

Phase slew control (for hitless reference switching)

•

Tuning word history control (for holdover operation)

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