AD9547SLASHPCBZ datasheet(46/104 Pages) AD

46 / 104 page

AD9547

Rev. 0 | Page 46 of 104

The controller decodes the number of bytes to transfer directly

from the data instruction itself by adding one to the value of the

instruction. For example, the data instruction, 0x1A, has a decimal

value of 26; therefore, the controller knows to transfer 27 bytes

(one more than the value of the instruction). Whenever the con-

troller encounters a data instruction, it knows to read the next

two bytes in the scratch pad because these bytes contain the

EEPROM

EEPROM Overview

The AD9547 contains an integrated 2048-byte electrically erasable

programmable read-only memory (EEPROM). The AD9547

can be configured to perform a download at power-up via the

multifunction pins (M3 to M7), but uploads and downloads

can also be done on demand via the EEPROM control registers

(Address 0x0E00 to Address 0x0E03).

Note that, in the EEPROM scratch pad, the two registers that

make up the address portion of a data instruction have the MSB of

the address in the D7 position of the lower register address. The

bit weight increases left to right, from the lower register address

to the higher register address. Furthermore, the starting address

always indicates the lowest numbered register map address in the

range of bytes to transfer. That is, the controller always starts at

the register map target address and counts upward, regardless of

whether the serial I/O port is operating in I2C, SPI LSB first, or

SPI MSB first mode.

The EEPROM provides the ability to upload and download

configuration settings to and from the register map. Figure 47

shows a functional diagram of the EEPROM.

pad that enables the user to store a sequence of instructions for

transferring data to the EEPROM from the device settings portion

of the register map. Note that the default values for these registers

provide a sample sequence for saving/retrieving all of the AD9547

EEPROM-accessible registers. Figure 47 shows the connectivity

between the EEPROM and the controller that manages data

transfer between the EEPROM and the register map.

As part of the data transfer process during an EEPROM upload,

the controller calculates a 1-byte checksum and stores it as the final

byte of the data transfer. As part of the data transfer process during

an EEPROM download, however, the controller again calculates

a 1-byte checksum value but compares the newly calculated check-

sum with the one that was stored during the upload process. If an

upload/download checksum pair does not match, the controller

sets the EEPROM fault status bit (Register 0x0D03, Bit 1). If the

upload/download checksums match for all data instructions

encountered during a download sequence, the controller sets

the EEPROM complete status bit (Register 0x0D03, Bit 0).

The controller oversees the process of transferring EEPROM data

to and from the register map. There are two modes of operation

handled by the controller: saving data to the EEPROM (upload

mode) or retrieving data from the EEPROM (download mode).

In either case, the controller relies on a specific instruction set.

EEPROM

(0x000 TO 0x7FF)

DATA

EEPROM

ADDRESS

POINTER

DEVICE SETTINGS

(0x0100 TO 0x0A10)

SCRATCH PAD

(0x0E10 TO 0x0E3F)

SERIAL

INPUT/OUTPUT

PORT

SCRATCH PAD

ADDRESS

POINTER

DEVICE

SETTINGS

ADDRESS

POINTER

EEPROM

CONTROLLER

Condition instructions are those that have a value from 0xB0 to

0xCF. Condition Instruction 0xB1 to Condition Instruction 0xCF

represent Condition 1 to Condition 31, respectively. Condition

Instruction 0xB0 is special because it represents the null condition

(see the EEPROM Conditional Processing section).

A pause instruction, like an end instruction, is stored at the end

of a sequence of instructions in the scratch pad. When the control-

ler encounters a pause instruction during an upload sequence,

it keeps the EEPROM address pointer at its last value. This way,

the user can store a new instruction sequence in the scratch pad

and upload the new sequence to the EEPROM. The new sequence

is stored in the EEPROM address locations immediately following

the previously saved sequence. This process is repeatable until

an upload sequence contains an end instruction. The pause

instruction is also useful when used in conjunction with condition

processing. It allows the EEPROM to contain multiple occurrences

of the same register(s), with each occurrence linked to a set of

conditions (see the EEPROM Conditional Processing section).

Figure 47. EEPROM Functional Diagram

EEPROM Instructions

Table 27 lists the EEPROM controller instruction set. The

controller recognizes all instruction types, whether it is in

upload or download mode, except for the pause instruction,

which it recognizes only in upload mode.

The I/O update, calibrate, distribution sync, and end instruc-

tions are mostly self-explanatory. The others, however, warrant

further detail, as described in the following paragraphs.

Data instructions are those that have a value from 0x00 to 0x7F.

A data instruction tells the controller to transfer data between

the EEPROM and the register map. The controller needs the

following two parameters to carry out the data transfer:

•

The number of bytes to transfer

•

The register map target address

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