AD9547SLASHPCBZ datasheet(42/104 Pages) AD

42 / 104 page

AD9547

Rev. 0 | Page 42 of 104

Active Reference Synchronization (Zero Delay)

Active reference synchronization is the term applied to the case

when sync source = 01 (Register 0x0402, Bits[5:4]). Referring to

Figure 46, this means that the active reference sync path is active

because Bit 4 = 1, enabling the lower AND gate and disabling

the upper AND gate. The edge detector in the active reference

sync block monitors the rising edges of the active reference

(the mux selects the active reference automatically). The edge

detector is armed via the primary synchronization signal, which

is one of the four inputs to the OR gate (typically the direct sync

source). As soon as the edge detector is armed, its output goes high,

which stalls the output dividers in the clock distribution block.

Furthermore, once armed, a rising edge from the active reference

forces the output of the edge detector low. This restarts the output

dividers, thereby synchronizing the clock distribution block.

The term zero delay applies because it provides a means to edge-

align the output signal with the active input reference signal.

Typically, zero-delay architectures use the output signal in the

feedback loop of a PLL to track input/output edge alignment.

Active reference synchronization, however, operates open loop.

That is, synchronization of the output via the distribution

synchronization logic occurs on a single edge of the active

reference.

The fact that an active reference edge triggers the falling edge of

the synchronization pulse means that the falling edge is asynchro-

nous to the signal that clocks the distribution output dividers

(CLKINx). Therefore, the output clock distribution logic reclocks

the internal synchronization pulse to synchronize it with the

CLKINx signal. This means that the output dividers restart after

a deterministic delay associated with the reclocking circuitry.

This deterministic delay has two components. The first deter-

ministic delay component is four or five periods of the CLKINx

signal. The one period uncertainty is due to the unknown position

of the asynchronous reference clock edge relative to the CLKINx

signal. The second deterministic delay component is one output

period of the distribution divider.

MULTIFUNCTION PIN

SYNC SOURCE

0x0402[5]

SYSCLK/4

DPLL

FEEDBACK

EDGE

0x0402[4]

REF A

REF BB

RESET

EDGE

DETECT

EDGE

DETECT

ARM

EDGE

DETECT

ARM

DIRECT SYNC

DPLL EDGE SYNC

ACTIVE REFERENCE SYNC

EEPROM SYNC

SOURCE

PRIMARY

SYNCHRONIZATION

SIGNAL

DIRECT SYNC

SOURCE

(ADDRESS DX 0x0A02[1])

AUTOMATIC SYNC

SOURCE

(REGISTER DX 0x0403)

TO CLOCK

DISTRIBUTION

SYNCHRONIZATION

CONTROL

STALL

DIVIDERS

SYNC OUTPUT

DISTRIBUTION

TO MULTIFUNCTION

PIN STATUS LOGIC

Figure 46. Output Synchronization Block Diagram

AD9547/PCBZ 数据表(PDF) 42 Page - Analog Devices

AD9547/PCBZ 数据表(HTML) 42 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载

链接网址

AD9547/PCBZ 数据表(PDF) 42 Page - Analog Devices

AD9547/PCBZ 数据表(HTML) 42 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表 下载

链接网址

数据表下载