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AD9547/PCBZ 数据表(PDF) 66 Page - Analog Devices

部件名 AD9547/PCBZ
功能描述  Dual/Quad Input Network Clock Generator/Synchronizer
PDF  104 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

AD9547/PCBZ 数据表(HTML) 66 Page - Analog Devices

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AD9547
Rev. 0 | Page 66 of 104
Addr
Opt1
Name
D7
D6
D5
D4
D3
D2
D1
D0
Def
0x0E19
E
Address: 0x0300
0x03
0x0E1A
E
0x00
0x0E1B
E
Clock
distribution
settings
Data: 26 bytes
0x19
0x0E1C
E
Address: 0x0400
0x04
0x0E1D
E
0x00
0x0E1E
E
I/O update
Action: I/O update
0x80
0x0E1F
E
Reference
input settings
Data: 8 bytes
0x07
0x0E20
E
Address: 0x0500
0x05
0x0E21
E
0x00
0x0E22
E
Profile 0 and
Profile 1
settings
Data: 100 bytes
0x63
0x0E23
E
Address: 0x0600
0x06
0x0E24
E
0x00
0x0E25
E
Profile2 and
Profile 3
settings
Data: 100 bytes
0x63
0x0E26
E
Address: 0x0680
0x06
0x0E27
E
0x80
0x0E28
E
Profile 4 and
Profile 5
settings
Data: 100 bytes
0x63
0x0E29
E
Address: 0x0700
0x07
0x0E2A
E
0x00
0x0E2B
E
Profile 6 and
Profile 7
settings
Data: 100 bytes
0x63
0x0E2C
E
Address: 0x0780
0x07
0x0E2D
E
0x80
0x0E2E
E
I/O update
Action: I/O update
0x80
0x0E2F
E
Operational
control
settings
Data: 17 bytes
0x10
0x0E30
E
Address: 0x0A00
0x0A
0x0E31
E
0x00
0x0E32
E
I/O update
Action: I/O update
0x80
0x0E33
E
End of data
Action: end of data
0xFF
0x0E34
to
0x0E3F
E
Continuation of scratch pad area
1 See the I/O Programming Registers section for an explanation of the Opt column.



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