AD9547SLASHPCBZ datasheet(38/104 Pages) AD

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AD9547

Rev. 0 | Page 38 of 104

The LF path permits the user to provide an LVPECL, LVDS,

CMOS, or sinusoidal low frequency clock for multiplication

by the integrated SYSCLK PLL. The LF path handles input

frequencies from 3.5 MHz up to 100 MHz. However, when

using a sinusoidal input signal, it is best to use a frequency in

excess of 20 MHz. Otherwise, the resulting low slew rate can

lead to substandard noise performance. Note that the LF path

includes an optional 2× frequency multiplier to double the rate

at the input to the SYSCLK PLL and potentially reduce the PLL

in-band noise. However, to avoid exceeding the maximum PFD

rate of 150 MHz, use of the 2× frequency multiplier is valid only

for input frequencies below 125 MHz.

The XTAL path enables the connection of a crystal resonator

(typically 10 MHz to 50 MHz) across the SYSCLKx input pins.

An internal amplifier provides the negative resistance required

to induce oscillation. The internal amplifier expects a 3.2 mm ×

2.5 mm AT cut, fundamental mode crystal with a maximum

motional resistance of 100 Ω. The following crystals, listed in

alphabetical order, may meet these criteria. Note that, although

these crystals meet the preceding criteria according to their data

sheets, Analog Devices, Inc., does not guarantee their opera-tion

with the AD9547, nor does Analog Devices endorse one crystal

manufacturer/supplier over another.

•

AVX/Kyocera CX3225SB

•

ECS ECX-32

•

Epson/Toyocom TSX-3225

•

NDK NX3225SA

•

Siward SX-3225

SYSCLK PLL MULTIPLIER

The SYSCLK PLL multiplier is an integer-N design and relies on

an integrated LC tank and VCO. It provides a means to convert

a low frequency clock input to the desired system clock frequency,

fS (900 MHz to 1 GHz). The SYSCLK PLL multiplier accepts input

signals between 3.5 MHz and 500 MHz, but frequencies in excess

of 150 MHz require the M-divider to ensure compliance with

the maximum PFD rate (150 MHz). The PLL contains a feedback

divider (N) that is programmable for divide values between 6 and

255. The nominal VCO gain is 70 MHz/V.

Lock Detector

The SYSCLK PLL has a built-in lock detector. Register 0x0100,

Bit 2 determines whether the lock detector is active. When it

is active (default), the user controls the sensitivity of the lock

detector via the lock detect divider bits (Register 0x0100, Bits[1:0]).

Note that a value of zero must be written to the system clock

stability timer (Register 0x0106 to Register 0x0108) whenever

the lock detector is disabled (Register 0x0100, Bit 2 = 1).

The SYSCLK PLL phase detector operates at the PFD rate, which is

fVCO/N. Each PFD sample indicates whether the reference and feed-

back signals are phase aligned (within a certain threshold range).

While the PLL is in the process of acquiring a lock condition,

the PFD samples typically consist of an arbitrary sequence of

in-phase and out-of-phase indications. As the PLL approaches

complete phase lock, the number of consecutive in-phase PFD

samples grows larger. Thus, one way of indicating a locked

condition is to count the number of consecutive in-phase PFD

samples and, if it exceeds a certain value, declare the PLL locked.

This is exactly the role of the lock detect divider bits. When the

lock detector is enabled (Register 0x0100, Bit 2 = 0), the lock detect

divider bits determine the number of consecutive in-phase deci-

sions that are required (128, 256, 512, or 1024) before the lock

detector declares a locked condition. The default setting is 128.

Charge Pump

The charge pump operates in either automatic or manual mode,

based on the charge pump mode bit (Register 0x0100, Bit 6).

When Register 0x0100, Bit 6 = 0, the AD9547 automatically selects

the appropriate charge pump current based on the N divider value.

Note that the user does not have control of the charge pump cur-

rent bits (Register 0x0100, Bits[5:3]) in automatic mode. When

current via the charge pump current bits (Register 0x0100,

Bits[5:3]). The charge pump current varies from 125 μA to 1 mA

in 125 μA steps. The default setting is 500 μA.

SYSCLK PLL Loop Filter

The AD9547 has an internal second-order loop filter that estab-

lishes the loop dynamics for input signals between 12.5 MHz and

100 MHz. By default, the device uses the internal loop filter.

However, an external loop filter option is available by setting

the external loop filter enable bit (Register 0x0100, Bit 7). This

bit bypasses the internal loop filter and allows the device to use

an externally connected second-order loop filter, as shown in

Figure 44.

SYSCLK_VREG

AD9547

SYSCLK_LF

Figure 44. External Loop Filter Schematic

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