 |
数据搜索系统，热门电子元器件搜索 |
|
|
数据搜索系统，热门电子元器件搜索 |
|
AD9547/PCBZ 数据表(PDF) 72 Page - Analog Devices |
|
|
|||||||||||||||||||||||||||||
AD9547/PCBZ 数据表(HTML) 72 Page - Analog Devices |
|
|
72 / 104 page  AD9547 Rev. 0 | Page 72 of 104 DPLL CONFIGURATION (REGISTER 0x0300 TO REGISTER 0x031B) Table 57. Free-Running Frequency Tuning Word1 Address Bit Bit Name Description 0x0300 [7:0] Free-running frequency tuning word (expressed as a 48-bit frequency tuning word) Free-running frequency tuning word, Bits[7:0]. 0x0301 [7:0] Free-running frequency tuning word, Bits[15:8]. 0x0302 [7:0] Free-running frequency tuning word, Bits[23:16]. 0x0303 [7:0] Free-running frequency tuning word, Bits[31:24]. 0x0304 [7:0] Free-running frequency tuning word, Bits[39:32]. 0x0305 [7:0] Free-running frequency tuning word, Bits[47:40]. 1 The default free-running tuning word is 0x000000 = 0, which equates to 0 Hz. Table 58. Update TW Address Bit Bit Name Description 0x0306 [7:1] Unused Unused. 0 Update TW A Logic 1 written to this bit transfers the free-running frequency tuning word (Register 0x0300 to Register 0x0305) to the register embedded in the tuning word processing logic. Note that it is not necessary to write the update TW bit when the device is in free-run mode. This is an autoclearing bit. Table 59. Pull-in Range Lower and Upper Limit1 Address Bit Bit Name Description 0x0307 [7:0] Pull-in range lower limit (expressed as a 24-bit frequency tuning word) Lower limit pull-in range, Bits[7:0]. 0x0308 [7:0] Lower limit pull-in range, Bits[15:8]. 0x0309 [7:0] Lower limit pull-in range, Bits[23:16]. 0x030A [7:0] Pull-in range upper limit (expressed as a 24-bit frequency tuning word) Upper limit pull-in range, Bits[7:0]. 0x030B [7:0] Upper limit pull-in range, Bits[15:8]. 0x030C [7:0] Upper limit pull-in range, Bits[23:16]. 1 The default pull-in range lower limit is 0 and the upper range limit is 0xFFFFFF, which effectively spans the full output frequency range of the DDS. Table 60. Open-Loop Phase Offset1 Address Bit Bit Name Description 0x030D [7:0] Open-loop phase offset (expressed in units of π/215 radians) DDS phase offset, Bits[7:0]. 0x030E [7:0] DDS phase offset, Bits[15:8]. 1 The default DDS phase offset is 0. Table 61. Fixed Closed-Loop Phase Lock Offset1 Address Bit Bit Name Description 0x030F [7:0] Fixed phase lock offset (expressed in ps) Fixed phase lock offset, Bits[7:0]. 0x0310 [7:0] Fixed phase lock offset, Bits[15:8]. 0x0311 [7:0] Fixed phase lock offset, Bits[23:16]. 0x0312 [7:0] Fixed phase lock offset, Bits[31:24]. 0x0313 [7:0] Fixed phase lock offset, Bits[39:32]. 1 The default fixed closed loop phase lock offset is 0. |
|
链接网址 |
| ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 数据表链接 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Chinese ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
