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AD9547

Rev. 0 | Page 32 of 104

DIGITAL PHASE-LOCKED LOOP (DPLL) CORE

DPLL Overview

A diagram of the digital PLL core of the AD9547 appears in

Figure 35. The phase/frequency detector, feedback path, lock

detectors, phase offset, and phase slew rate limiting that make

up this second-generation DPLL are all digital implementations.

R + 1

REF A

TDC

AND

PFD

DIGITAL

LOOP

FILTER

DDS/

DAC

DACOUT

CLOSED-LOOP

PHASE OFFSET

PHASE SLEW

LIMIT

LOCK

DETECT

REF BB

DPPL CORE

fREF

fTDC

fDDS

S + 1 + U/V

Figure 35. Digital PLL Core

The start of the DPLL signal chain is the reference signal, fREF,

which is the frequency of the reference input. A reference

prescaler reduces the frequency of this signal by an integer

factor, R + 1, where R is the 30-bit value stored in the profile

the output of the R divider (or the input to the time-to-digital

converter (TDC)) is

REF

TDC

The TDC samples the output of the R divider. The TDC/PFD

produces a time series of digital words and delivers them to the

digital loop filter. The digital loop filter offers the following

advantages:

•

Determination of the filter response by numeric

coefficients rather than by discrete component values

•

Absence of analog components (R/L/C), which eliminates

tolerance variations due to aging

•

Absence of thermal noise associated with analog

components

•

Absence of control node leakage current associated with

analog components (a source of reference feed-through

spurs in the output spectrum of a traditional analog PLL)

The digital loop filter produces a time series of digital words

at its output and delivers them to the frequency tuning input of

a direct digital synthesizer (DDS), with the DDS replacing the

function of the VCO in an analog PLL. The digital words from

the loop filter tend to steer the DDS frequency toward frequency

and phase lock with the input signal (fTDC). The DDS provides

an analog output signal via an integrated DAC, effectively

mimicking the operation of an analog VCO.

The DPLL includes a feedback divider that causes the DDS to

operate at an integer-plus-fractional multiple (S + 1 + U/V) of

fTDC. S is the 20-bit value stored in the profile register and has a

range of 7 ≤ S ≤ 1,048,576. U and V are the 10-bit numerator

and denominator values of the optional fractional divide

component, also stored in the profile register. Together they

establish the nominal DDS frequency (fDDS), given by

⎟

⎠

⎞

⎜

⎝

⎛

REF

DDS

Normally, fractional-N designs exhibit distinctive phase noise

and spurious artifacts resulting from the modulation of the

integer divider based on the fractional value. This is not the

case for the AD9547 because it uses a purely digital means to

determine phase errors. Because the phase errors incurred by

modulating the feedback divider are deterministic, it is possible

to compensate for them digitally. The result is a fractional-N

PLL with no discernible modulation artifacts.

Time-to-Digital Converter (TDC)/Phase Frequency

Detector (PFD)

The TDC is a highly integrated functional block that incorporates

both analog and digital circuitry. There are two pins associated

with the TDC that the user must connect to external components.

Figure 36 shows the recommended component values and their

connections.

For best performance, place components as close as possible to

the device pins. Components with low effective series resistance

(ESR) and low parasitic inductance yield the best results.

AD9547

10µF

0.1µF

TDC_VRT

TDC_VRB

Figure 36. TDC Pin Connections

The PFD is an all-digital block. It compares the digital output

from the TDC (which relates to the active reference edge) with

the digital word from the feedback block (which relates to the

rollover edge of the DDS accumulator after division by the feed-

back divider). The PFD uses a digital code pump and digital

integrator (rather than a conventional charge pump and capacitor)

to generate the error signal that steers the DDS frequency toward

phase lock.

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