 |
数据搜索系统，热门电子元器件搜索 |
|
|
数据搜索系统，热门电子元器件搜索 |
|
AD9547/PCBZ 数据表(PDF) 53 Page - Analog Devices |
|
|
|||||||||||||||||||||||||||||
AD9547/PCBZ 数据表(HTML) 53 Page - Analog Devices |
|
|
53 / 104 page  AD9547 Rev. 0 | Page 53 of 104 DATA BIT N – 1 DATA BIT N CS SCLK SDIO SDO tDV Figure 54. Serial Control Port Timing—Read CS SCLK DON'T CARE DON'T CARE 16-BIT INSTRUCTION HEADER REGISTER (N) DATA REGISTER (N + 1) DATA SDIO DON'T CARE DON'T CARE A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 D1 D0 R/W W1 W0 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 Figure 55. Serial Control Port Write—LSB First, 16-Bit Instruction, Two Bytes of Data CS SCLK SDIO tHIGH tLOW tCLK tS tDS tDH tC BIT N BIT N + 1 Figure 56. Serial Control Port Timing—Write Table 33. Serial Control Port Timing Parameter Description tDS Setup time between data and the rising edge of SCLK tDH Hold time between data and the rising edge of SCLK tCLK Period of the clock tS Setup time between the CS falling edge and SCLK rising edge (start of the communication cycle) tC Setup time between the SCLK rising edge and CS rising edge (end of the communication cycle) tHIGH Minimum period that SCLK should be in a logic high state tLOW Minimum period that SCLK should be in a logic low state tDV SCLK to valid SDIO and SDO (see Figure 54) |
|
链接网址 |
| ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 数据表链接 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Chinese ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
