AD9547SLASHPCBZ datasheet(91/104 Pages) AD

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AD9547

Rev. 0 | Page 91 of 104

Table 127. Incremental Phase Offset Control

Address

Bit

Bit Name

Description

0x0A0C

[7:3]

Unused

Unused.

Reset phase offset

Resets the incremental phase offset to 0. This is an autoclearing bit.

Decrement phase offset

Decrements the incremental phase offset by the amount specified in the incremental

phase lock offset step size register (Register 0x0314 to Register 0x0315).

This is an autoclearing bit.

Increment phase offset

Increments the incremental phase offset by the amount specified in the incremental phase

lock offset step size register (Register 0x0314 to Register 0x0315).

This is an autoclearing bit.

Table 128. Reference Profile Selection State Machine Startup1

Address

Bit

Bit Name

Description

0x0A0D

[7:4]

Unused

Unused.

Detect BB

Setting this bit starts the profile selection state machine for Input Reference BB.

Detect B

Setting this bit starts the profile selection state machine for Input Reference B.

Detect AA

Setting this bit starts the profile selection state machine for Input Reference AA.

Detect A

Setting this bit starts the profile selection state machine for Input Reference A.

1 All bits in this register are autoclearing.

Table 129. Force Validation Timeout1

Address

Bit

Bit Name

Description

0x0A0E

[7:4]

Unused

Unused.

Force Timeout BB

Setting this bit emulates timeout of the validation timer for Reference BB.

This is an autoclearing bit.

Force Timeout B

Setting this bit emulates timeout of the validation timer for Reference B.

This is an autoclearing bit.

Force Timeout AA

Setting this bit emulates timeout of the validation timer for Reference AA.

This is an autoclearing bit.

Force Timeout A

Setting this bit emulates timeout of the validation timer for Reference A.

This is an autoclearing bit.

1 All bits in this register are autoclearing.

Table 130. Reference Monitor Override1

Address

Bit

Bit Name

Description

0x0A0F

[7:4]

Unused

Unused.

Ref Mon Override BB

Overrides the reference monitor REF fault signal for Reference BB (default = 0, not overridden).

Ref Mon Override B

Overrides the reference monitor REF fault signal for Reference B (default = 0, not overridden).

Ref Mon Override AA

Overrides the reference monitor REF fault signal for Reference AA (default = 0, not overridden).

Ref Mon Override A

Overrides the reference monitor REF fault signal for Reference A (default = 0, not overridden).

1 All bits in this register are autoclearing.

Table 131. Reference Monitor Bypass1

Address

Bit

Bit Name

Description

0x0A10

[7:4]

Unused

Unused.

Ref Mon Bypass BB

Bypasses the reference monitor for Reference BB (default = 0, not bypassed).

Ref Mon Bypass B

Bypasses the reference monitor for Reference B (default = 0, not bypassed).

Ref Mon Bypass AA

Bypasses the reference monitor for Reference AA (default = 0, not bypassed).

Ref Mon Bypass A

Bypasses the reference monitor for Reference A (default = 0, not bypassed).

1 All bits in this register are autoclearing.

AD9547/PCBZ 数据表(PDF) 91 Page - Analog Devices

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AD9547/PCBZ 数据表(PDF) 91 Page - Analog Devices

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