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数据搜索系统，热门电子元器件搜索 |
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WM8944BECS/R 数据表(PDF) 44 Page - Cirrus Logic |
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WM8944BECS/R 数据表(HTML) 44 Page - Cirrus Logic |
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44 / 165 page  WM8944B 44 Rev 4.3 GAIN READBACK The gain applied by the DRC can be read from the DRC_GAIN register. This is a 16-bit, fixed-point value, which expresses the DRC gain as a voltage multiplier. DRC_GAIN is coded as a fixed-point quantity, with an MSB weighting of 64. The first 7 bits represent the integer portion; the remaining bits represent the fractional portion. If desired, the value of this field may be interpreted by treating DRC_GAIN as an integer value, and dividing the result by 512, as illustrated in the following examples: DRC_GAIN = 05D4 (hex) = 1380 (decimal) Divide by 512 gives 2.914 voltage gain, or 4.645dB DRC_GAIN = 0100 (hex) = 256 (decimal) Divide by 512 gives 0.5 voltage gain, or -3.01dB The DRC_GAIN register is defined in Table 20. REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R36 (24h) DRC Status (Read only) 15:0 DRC_GAIN [15:0] DRC Gain value (Read only). This is the DRC gain, expressed as a voltage multiplier. Fixed point coding, MSB = 64. The first 7 bits are the integer portion; the remaining bits are the fractional part. Table 20 DRC Gain Readback |
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