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WM8944BECS/R 数据表(PDF) 37 Page - Cirrus Logic |
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WM8944BECS/R 数据表(HTML) 37 Page - Cirrus Logic |
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37 / 165 page  WM8944B Rev 4.3 37 DYNAMIC RANGE CONTROL (DRC) DRC Signal Enhancement Block 3 (SE3) The Dynamic Range Control (DRC) forms the SE3 block. The DRC provides a range of compression, limiting and noise gate functions to support optimum configuration for recording or playback modes. The DRC is configured using the control fields in registers R29 to R35 - see “Dynamic Range Control”. SIGNAL ENHANCEMENT REGISTER CONTROLS The SE1 ‘enable’ bits are described in Table 13. Note that other control fields must also be determined and written to the WM8944B using WISCE™ or other tools. The registers described below only allow the sub-blocks of SE1 to be enabled or disabled. Note that it is not recommended to access these control fields unless appropriate values have been written to the associated bits in registers R65 to R95. REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R65 (41h) SE1_LHPF_C ONFIG 1 SE1_LHPF_R_E NA 0 SE1 Right channel low-pass / high- pass filter enable 0 = Disabled 1 = Enabled 0 SE1_LHPF_L_E NA 0 SE1 Left channel low-pass / high- pass filter enable 0 = Disabled 1 = Enabled R68 (41h) SE1_3D_CON FIG 1 SE1_3D_R_ENA 0 SE1 Right channel 3D stereo enhancement enable 0 = Disabled 1 = Enabled 0 SE1_3D_L_ENA 0 SE1 Left channel 3D stereo enhancement enable 0 = Disabled 1 = Enabled R71 (47h) SE1_NOTCH_ CONFIG 1 SE1_NOTCH_R _ENA 0 SE1 Right channel notch filters enable 0 = Disabled 1 = Enabled 0 SE1_NOTCH_L_ ENA 0 SE1 Left channel notch filters enable 0 = Disabled 1 = Enabled R92 (5Ch) SE1_DF1_CO NFIG 1 SE1_DF1_R_EN A 0 SE1 Right channel DF1 filter enable 0 = Disabled 1 = Enabled 0 SE1_DF1_L_EN A 0 SE1 Left channel DF1 filter enable 0 = Disabled 1 = Enabled Table 13 Signal Enhancement Block 1 (SE1) |
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