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WM8944BECS/R 数据表(PDF) 18 Page - Cirrus Logic

部件名 WM8944BECS/R
功能描述  Mono Low-Power CODEC with Video Buffer
PDF  165 Pages
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制造商  CIRRUS [Cirrus Logic]
网页  http://www.cirrus.com
标志 CIRRUS - Cirrus Logic

WM8944BECS/R 数据表(HTML) 18 Page - Cirrus Logic

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WM8944B
18
Rev 4.3
SLAVE MODE
BCLK (input)
LRCLK (input)
ADCDAT (output)
DACDAT (input)
tDS
tDD
tDH
tLRH
tLRSU
tBCH
tBCL
tBCY
Figure 4 Audio Interface Timing
– Slave Mode
Test Conditions
DCVDD = 1.8V, DBVDD = LDOVDD = SPKVDD = 3.3V, LDOVOUT = 3.0V, GND = 0V,
TA = +25
oC, 1kHz signal, fs = 48kHz, PGA gain = 0dB, 24-bit audio data unless otherwise stated.
PARAMETER
SYMBOL
MIN
TYP
MAX
UNIT
Audio Interface Timing - Slave Mode
BCLK cycle time
tBCY
50
ns
BCLK pulse width high
tBCH
20
ns
BCLK pulse width low
tBCL
20
ns
LRCLK set-up time to BCLK rising edge
tLRSU
20
ns
LRCLK hold time from BCLK rising edge
tLRH
10
ns
DACDAT hold time from BCLK rising edge
tDH
10
ns
ADCDAT propagation delay from BCLK falling edge
tDD
20
ns
DACDAT set-up time to BCLK rising edge
tDS
20
ns
Note: BCLK period must always be greater than or equal to MCLK period.



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