WM8944BECSSLASHR datasheet(77/165 Pages) CIRRUS

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WM8944B

Rev 4.3

DIGITAL MIC CLOCKING

When any GPIO is configured as DMICCLK output, the WM8944B outputs a clock which supports

Digital Mic operation at the ADC sampling rate. Although the ADC is not used, the SYSCLK and

Sample Rate control fields must still be set as they would for ADC operation.

The clock frequencies for each of the sample rates is shown in Table 52.

PCM SAMPLE RATE

DMICCLK

FS RATE

8kHz

1.024MHz

128fs

11.025kHz

1.411MHz

128fs

12kHz

1.536MHz

128fs

16kHz

2.048MHz

128fs

22.05kHz

2.8224MHz

128fs

24kHz

3.072MHz

128fs

32kHz

2.048MHz

64fs

44.1kHz

2.8224MHz

64fs

48kHz

3.072MHz

64fs

Table 52 Digital Microphone Clock Frequencies

FREQUENCY LOCKED LOOP (FLL)

The integrated FLL can be used to generate SYSCLK from a wide variety of different reference

sources and frequencies. The FLL uses MCLK as its reference, which may be a high frequency (eg.

12.288MHz) or low frequency (eg. 32,768kHz) reference. The FLL is tolerant of jitter and may be used

to generate a stable SYSCLK from a less stable input signal. The FLL characteristics are summarised

in “Electrical Characteristics”.

The FLL control registers are described in Figure 32.

FVCO

FOUT

90MHz < Fvco < 100MHz

FLL_OUTDIV = 4, 8, 16, 32

FLL_FRATIO = 1, 2, 4, 8, 16

Multiply by

N.K

N.K = Real number

Divide by

FLL_CLK_REF_DIV

FREF

FLL_CLK_REF_DIV = 1, 2, 4, 8

FREF<13.5MHz

Divide by

FLL_OUTDIV

Multiply by

FLL_FRATIO

MCLK

Figure 32 FLL Configuration

The FLL is enabled using the FLL_ENA register bit. Note that, when changing FLL settings, it is

recommended that the digital circuit be disabled via FLL_ENA and then re-enabled after the other

recommended that the FLL be reset by setting FLL_ENA to 0.

The field FLL_CLK_REF_DIV provides the option to divide the input reference (MCLK) by 1, 2, 4 or 8.

This field should be set to bring the reference down to 13.5MHz or below. For best performance, it is

recommended that the highest possible frequency

– within the 13.5MHz limit – should be selected.

The field FLL_CTRL_RATE controls internal functions within the FLL; it is recommended that only the

default setting be used for this parameter. FLL_GAIN controls the internal loop gain and should be set

to the recommended value.

The FLL output frequency is directly determined from FLL_FRATIO, FLL_OUTDIV and the real

number represented by FLL_N and FLL_K. The field FLL_N is an integer (LSB = 1); FLL_K is the

fractional portion of the number (MSB = 0.5). The fractional portion is only valid when enabled by the

field FLL_FRAC.

Power consumption in the FLL is reduced in integer mode; however, the performance may also be

reduced, with increased noise or jitter on the output.

If low power consumption is required, then FLL settings must be chosen where N.K is an integer (ie.

FLL_K = 0). In this case, the fractional mode can be disabled by setting FLL_FRAC = 0.

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