WM8944BECSSLASHR datasheet(76/165 Pages) CIRRUS

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WM8944B

Rev 4.3

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

CLKOUT_SEL

CLKOUT Source Select

0 = SYSCLK

1 = FLL or MCLK (set by

SYSCLK_SRC register)

11:10

CLKOUT_DIV

[1:0]

CLKOUT Clock divider

00 = divide by 1

01 = divide by 2

10 = divide by 4

11 = divide by 8

SYSCLK_ENA

SYSCLK Enable

0 = Disabled

1 = Enabled

SYSCLK_SRC

SYSCLK Source Select

0 = MCLK

1 = FLL output

7:5

SYSCLK_DIV

[2:0]

000

SYSCLK Clock divider

(Sets the scaling for either the

MCLK or FLL clock output,

depending on SYSCLK_SRC)

000 = divide by 1

001 = divide by 1.5

010 = divide by 2

011 = divide by 3

100 = divide by 4

101 = divide by 6

110 = divide by 8

111 = divide by 12

TOCLK_ENA

TOCLK Enabled

(Enables timeout clock for GPIO

level detection)

0 = Disabled

1 = Enabled

R7 (07h)

Additional

control

SYSCLK_RATE

Selects the SYSCLK / fs ratio

0 = SYSCLK = 256 x fs

1 = SYSCLK = 512 x fs

3:0

SR [3:0]

1101

Audio Sample Rate select

0011 = 8kHz

0100 = 11.025kHz

0101 = 12kHz

0111 = 16kHz

1000 = 22.05kHz

1001 = 24kHz

1011 = 32kHz

1100 = 44.1kHz

1101 = 48kHz

Table 51 Clocking and Sample Rate Control

WM8944BECS/R 数据表(PDF) 76 Page - Cirrus Logic

WM8944BECS/R 数据表(HTML) 76 Page - Cirrus Logic

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