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WM8944BECS/R 数据表(PDF) 96 Page - Cirrus Logic |
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WM8944BECS/R 数据表(HTML) 96 Page - Cirrus Logic |
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96 / 165 page  WM8944B 96 Rev 4.3 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION 11 SPKN_SPKVDD _ENA 0 SPKOUTN enable 0 = Disabled 1 = Enabled Note that SPKOUTN is also controlled by SPKN_OP_ENA. When powering down SPKOUTN, the SPKN_SPKVDD_ENA bit should be reset first. 10 SPKP_SPKVDD _ENA 0 SPKOUTP enable 0 = Disabled 1 = Enabled Note that SPKOUTP is also controlled by SPKP_OP_ENA. When powering down SPKOUTP, the SPKP_SPKVDD_ENA bit should be reset first 7 SPKN_OP_ENA 0 SPKOUTN enable 0 = Disabled 1 = Enabled Note that SPKOUTN is also controlled by SPKN_SPKVDD_ENA. When powering up SPKOUTN, the SPKN_OP_ENA bit should be enabled first. 6 SPKP_OP_ENA 0 SPKOUTP enable 0 = Disabled 1 = Enabled Note that SPKOUTP is also controlled by SPKP_SPKVDD_ENA. When powering up SPKOUTP, the SPKP_OP_ENA bit should be enabled first 2 SPK_MIX_ENA 0 Speaker output mixer enable 0 = Disabled 1 = Enabled 0 DAC_ENA 0 DAC Enable 0 = Disabled 1 = Enabled DAC_ENA must be set to 1 when processing data from the DAC or Digital Beep Generator. Table 67 Power Management Control Note: In 2-wire mode in order to achieve the minimum power down current from DBVDD the CIF_MODE pin should be configured as a GPIO pin by setting register R11 (0Bh) bit 0 high and configured as an input in register R14 (0Eh) bit 0 set high. Pull-up and pull-down resistors should be disabled in register R14 (0Eh) bits 14:13 set to 00. |
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