WM8944BECSSLASHR datasheet(98/165 Pages) CIRRUS

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WM8944B

Rev 4.3

DCVDD

LDOVDD

Vpora

Vpord_off

POR

Undefined

Internal POR

Internal POR active

Device Ready

Internal POR active

Vpora_on

Figure 43 Power On Reset Timing - DCVDD Enabled First

The POR

¯¯¯ signal is undefined until LDOVDD has exceeded the minimum threshold, Vpora Once this

threshold has been exceeded, POR

¯¯¯ is asserted low and the chip is held in reset. In this condition, all

writes to the control interface are ignored. Once LDOVDD and DCVDD have both reached their

respective power on thresholds, POR

¯¯¯ is released high, all registers are in their default state, and

writes to the control interface may take place.

Note that a minimum power-on reset period, TPOR, applies even if LDOVDD and DCVDD have zero

rise time. (This specification is guaranteed by design rather than test.)

On power down, POR

¯¯¯ is asserted low when LDOVDD or DCVDD falls below their respective power-

down thresholds.

Typical Power-On Reset parameters for the WM8944B are defined in Table 69.

SYMBOL

DESCRIPTION

MIN

TYP

MAX

UNIT

Vpora

Power-On undefined threshold (LDOVDD)

0.5

Vpora_on

Power-On threshold (LDOVDD/DBVDD)

1.17

Vpora_off

Power-Off threshold (LDOVDD/DBVDD)

1.13

Vpord_on

Power-On threshold (DCVDD)

0.66

Vpord_off

Power-Off threshold (DCVDD)

0.64

TPOR

Minimum Power-On Reset period

10.6

s

Table 69 Typical Power-On Reset Parameters

Separate Power-On Reset circuits are also implemented on the DBVDD and SPKVDD domains.

These circuits ensure correct device behaviour whenever these supplies are enabled or disabled.

WM8944BECS/R 数据表(PDF) 98 Page - Cirrus Logic

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