WM8944BECSSLASHR datasheet(46/165 Pages) CIRRUS

46 / 165 page

WM8944B

Rev 4.3

Figure 17 Decay Time vs Register Value Decay Rate

The decay rate register value read from the horizontal axis and the decay time (10%-90%) read from

the vertical axis.

For example, if DRC DRC_DCY = 743ms/6dB, then the estimate decay time (10%-90%) taken from

the graph is 1.0s.

ANTI-CLIP CONTROL

The DRC includes an Anti-Clip feature to avoid signal clipping when the input amplitude rises very

quickly. This feature uses a feed-forward technique for early detection of a rising signal level. Signal

clipping is avoided by dynamically increasing the gain attack rate when required. The Anti-Clip feature

is enabled using the DRC_ANTICLIP bit.

Note that the feed-forward processing increases the latency in the input signal path. The DRC Anti-

Clip control is described in Table 22.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R29 (1Dh)

DRC Control 1

DRC_ANTICLIP

DRC Anti-clip Enable

0 = Disabled

1 = Enabled

Table 22 DRC Anti-Clip Control

Note that the Anti-Clip feature operates entirely in the digital domain. It cannot be used to prevent

signal clipping in the analogue domain nor in the source signal. Analogue clipping can only be

prevented by reducing the analogue signal gain or by adjusting the source signal.

Note that the Anti-Clip and Quick Release features should not be used at the same time.

WM8944BECS/R 数据表(PDF) 46 Page - Cirrus Logic