| 数据搜索系统,热门电子元器件搜索 |
|
WM8944BECS/R 数据表(PDF) 70 Page - Cirrus Logic |
|
|
|||||||||||||||||||||||||||||
WM8944BECS/R 数据表(HTML) 70 Page - Cirrus Logic |
|
70 / 165 page ![]() WM8944B 70 Rev 4.3 n n-1 n-2 3 2 1 n n-1 n-2 3 2 1 LEFT CHANNEL RIGHT CHANNEL MSB LSB Input Word Length (WL) 1/fs LRCLK BCLK DACDAT/ ADCDAT 1 BCLK Falling edge can occur anywhere in this area 1 BCLK Figure 25 DSP/PCM Mode Audio Interface (mode A, LRCLK_INV=1, Slave) n n-1 n-2 3 2 1 n n-1 n-2 3 2 1 LEFT CHANNEL RIGHT CHANNEL MSB LSB Input Word Length (WL) 1/fs LRCLK BCLK DACDAT/ ADCDAT 1 BCLK 1 BCLK Falling edge can occur anywhere in this area Figure 26 DSP/PCM Mode Audio Interface (mode B, LRCLK_INV=1, Slave) COMPANDING The WM8944B supports A-law and -law companding on both transmit (ADC) and receive (DAC) sides as shown in Table 46. Companding converts 13 bits ( -law) or 12 bits (A-law) to 8 bits using non-linear quantization. This provides greater precision for low-amplitude signals than for high-amplitude signals, resulting in a greater usable dynamic range than 8 bit linear quantization. REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R5 (05h) Companding control 3 DAC_COMP 0 DAC Companding Enable 0 = Disabled 1 = Enabled 2 DAC_COMPMO DE 0 DAC Companding Mode 0 = µ-law 1 = A-law 1 ADC_COMP 0 ADC Companding Enable 0 = Disabled 1 = Enabled 0 ADC_COMPMO DE 0 ADC Companding Mode 0 = µ-law 1 = A-law Table 46 Companding Control |
|
链接网址 |
| ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 数据表链接 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |