WM8944BECSSLASHR datasheet(61/165 Pages) CIRRUS

61 / 165 page

WM8944B

Rev 4.3

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R7 (07h)

Additional

control

BIAS_SRC

Bias Source select

0 = Master bias

1 = Start-Up bias

R17 (11h)

Status Flags

LDO_UV_STS

LDO Undervoltage status (Read

only)

0 = Normal

1 = Undervoltage

R53 (35h)

LDO

LDO_ENA

LDO Enable

0 = Disabled

1 = Enabled

LDO_REF_SEL_F

AST

LDO Voltage reference select

0 = VMID (normal)

1 = VMID (fast start)

This field is only effective when

LDO_REF_SEL = 0

LDO_REF_SEL

LDO Voltage reference select

0 = VMID

1 = Bandgap

LDO_OPFLT

LDO Output float

0 = Disabled (Output discharged

when disabled)

1 = Enabled (Output floats when

disabled)

4:0

LDO_VSEL [4:0]

00111

LDO Voltage select

(Sets the LDO output as a ratio of

the selected voltage reference. The

voltage reference is set by

LDO_REF_SEL.)

00111 = Vref x 1.97 (default)

(See Table 38 for range)

R54 (36h)

Bandgap

BG_ENA

Bandgap Reference Control

0 = Disabled

1 = Enabled

4:0

BG_VSEL [4:0]

01010

Bandgap Voltage select

(Sets the Bnadgap voltage)

00000 = 1.200V

… 26.7mV steps

01010 = 1.467V (default)

…

01111 = 1.600V

10000 to 11111 = reserved

(See Table 39 for values)

Table 37 LDO Regulator Control

WM8944BECS/R 数据表(PDF) 61 Page - Cirrus Logic

WM8944BECS/R 数据表(HTML) 61 Page - Cirrus Logic

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载