WM8944BECSSLASHR datasheet(75/165 Pages) CIRRUS

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WM8944B

Rev 4.3

MCLK

fOUT

SYSCLK_SRC

SYSCLK_ENA

SYSCLK_DIV [2:0]

CODEC DSP

f/N

LRCLK

BCLK

MSTR

FLL

fREF

SR [3:0]

SYSCLK_RATE

CLKOUT_SEL

CLKOUT_DIV [1:0]

f/N

CLKOUT

CLKOUT may be

output on a GPIO pin

f/N

BCLK_DIV

[2:0]

MASTER

MODE

CLOCK

OUTPUTS

Oscillator

OSC_CLK_ENA

TOCLK_ENA

Clocking for GPIO de-bounce and Interrupt functions

Clocking for PGA Zero-Cross timeouts

f/64

FLL_ENA

FLL_CLK_REF_DIV

FLL_N

FLL_K

FLL_FRATIO

FLL_FRAC

FLL_OUTDIV

SYSCLK (512 x fs) or (256 x fs)

Figure 31 WM8944B Clocking Overview

SYSCLK may be derived either from MCLK or from the FLL; this is selected using the SYSCLK_SRC

divider configured by SYSCLK_DIV.

The SYSCLK_RATE register must be set according to the ratio of SYSCLK to the audio sample rate.

It is required that SYSCLK_DIV is correctly set in order to produce either 512 x fs or 256 x fs at its

output, where fs is the audio sampling rate.

The sampling rate for the CODEC and Digital Audio Interface is configured using the SR register field.

In Master mode, the frequency of the Left/Right Clock output on the LRCLK pin is the BCLK frequency

divided by 64 producing 32 BCLK cycles per channel. In Master mode, the BCLK_DIV register

configures the bit clock frequency output on BCLK.

The WM8944B can output a configurable clock on the GPIO pins; this is enabled automatically

whenever a GPIO pin is configured for CLKOUT output. The source can either be before or after the

SYSCLK divider, as shown in Figure 31. The source is selected using CLKOUT_SEL, and may be

modified using a programmable divider configured by CLKOUT_DIV.

The WM8944B free-running oscillator required for GPIO input de-bounce and Interrupt functions must

be enabled using OSC_CLK_ENA whenever any of these functions is required.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R6 (06h)

Clock Gen

control

OSC_CLK_ENA

Oscillator Enable

0 = Disabled

1 = Enabled

This needs to be set when a timeout

clock is required for GPIO input

detection

14:13

MCLK_PULL

[1:0]

MCLK pull-up / pull-down Enable

00 = no pull-up or pull-down

01 = pull-down

10 = pull-up

11 = reserved

WM8944BECS/R 数据表(PDF) 75 Page - Cirrus Logic

WM8944BECS/R 数据表(HTML) 75 Page - Cirrus Logic

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