WM8944BECSSLASHR datasheet(79/165 Pages) CIRRUS

79 / 165 page

WM8944B

Rev 4.3

In FLL Fractional Mode, the fractional portion of the N.K multiplier is held in the FLL_K register field.

This field is coded as a fixed point quantity, where the MSB has a weighting of 0.5. Note that, if

desired, the value of this field may be calculated by multiplying K by 2^16 and treating FLL_K as an

integer value, as illustrated in the following example:

If N.K = 8.192, then K = 0.192.

Multiplying K by 2^16 gives 0.192 x 65536 = 12582.912 (decimal)

Apply rounding to the nearest integer = 12583 (decimal) = 3127 (hex)

For best FLL performance, the FLL fractional mode is recommended. Therefore, if the calculations

yield an integer value of N.K, then it is recommended to adjust FLL_FRATIO in order to obtain a non-

integer value of N.K. Care must always be taken to ensure that the FLL operating frequency, FVCO, is

within its recommended limits of 90-100 MHz.

The register fields that control the FLL are described in Table 55. Example settings for a variety of

reference frequencies and output frequencies are shown in Table 56.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R8 (08h)

FLL Control 1

12:11

FLL_CLK_RE

F_DIV [1:0]

FLL Clock Reference Divider

00 = MCLK / 1

01 = MCLK / 2

10 = MCLK / 4

11 = MCLK / 8

MCLK must be divided down to

<=13.5MHz.

For lower power operation, the

reference clock can be divided down

further if desired.

10:8

FLL_OUTDIV

[2:0]

001

FOUT clock divider

000 = 2

001 = 4

010 = 8

011 = 16

100 = 32

101 = 64

110 = 6

111 = 12

(FOUT = FVCO / FLL_OUTDIV)

7:5

FLL_CTRL_R

ATE [2:0]

000

Frequency of the FLL control block

000 = FVCO / 1 (Recommended value)

001 = FVCO / 2

010 = FVCO / 3

011 = FVCO / 4

100 = FVCO / 5

101 = FVCO / 6

110 = FVCO / 7

111 = FVCO / 8

Recommended that this register is not

changed from default.

WM8944BECS/R 数据表(PDF) 79 Page - Cirrus Logic

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