WM8944BECSSLASHR datasheet(92/165 Pages) CIRRUS

92 / 165 page

WM8944B

Rev 4.3

2-WIRE (I2C) CONTROL MODE

In 2-wire mode, the WM8944B is a slave device on the control interface; SCLK is a clock input, while

SDA is a bi-directional data pin. To allow arbitration of multiple slaves (and/or multiple masters) on the

same interface, the WM8944B transmits logic 1 by tri-stating the SDA pin, rather than pulling it high.

An external pull-up resistor is required to pull the SDA line high so that the logic 1 can be recognised

by the master.

In order to allow many devices to share a single 2-wire control bus, every device on the bus has a

unique 8-bit device ID (this is not the same as the 15-bit address of each register in the WM8944B).

The WM8944B device ID is 0011 0100 (34h). The LSB of the device ID is the Read/Write bit; this bit is

set to logic 1 for “Read” and logic 0 for “Write”.

The WM8944B operates as a slave device only. The controller indicates the start of data transfer with

a high to low transition on SDA while SCLK remains high. This indicates that a device ID, register

address and data will follow. The WM8944B responds to the start condition and shifts in the next eight

bits on SDA (8-bit device ID including Read/Write bit, MSB first). If the device ID received matches the

device ID of the WM8944B, then the WM8944B responds by pulling SDA low on the next clock pulse

(ACK). If the device ID is not recognised or the R/W bit is ‘1’ when operating in write only mode, the

WM8944B returns to the idle condition and waits for a new start condition and valid address.

If the device ID matches the device ID of the WM8944B, the data transfer continues as described

below. The controller indicates the end of data transfer with a low to high transition on SDA while

SCLK remains high. After receiving a complete address and data sequence the WM8944B returns to

the idle state and waits for another start condition. If a start or stop condition is detected out of

sequence at any point during data transfer (i.e. SDA changes while SCLK is high), the device returns

to the idle condition.

The WM8944B supports the following read and write operations:



Single write



Single read



Multiple write using auto-increment



Multiple read using auto-increment

The sequence of signals associated with a single register write operation is illustrated in Figure 34.

A15

SDA

SCLK

device ID

data bits B15

– B8

B15

Note: The SDA pin is used as input for the control register address and data; SDA is

pulled low by the receiving device to provide the acknowledge (ACK) response

R/W

data bits B7

– B0

START

(Write)

ACK

STOP

ACK

Figure 34 Control Interface 2-wire (I2C) Register Write

The sequence of signals associated with a single register read operation is illustrated in Figure 35.

WM8944BECS/R 数据表(PDF) 92 Page - Cirrus Logic

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