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WM8944BECS/R 数据表(PDF) 74 Page - Cirrus Logic |
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WM8944BECS/R 数据表(HTML) 74 Page - Cirrus Logic |
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74 / 165 page  WM8944B 74 Rev 4.3 DIGITAL PULL-UP AND PULL-DOWN The WM8944B provides integrated pull-up and pull-down resistors on each of the DACDAT, LRCLK and BCLK pins. This provides a flexible capability for interfacing with other devices. Each of the pull- up and pull-down resistors can be configured independently using the register bits described in Table 50. REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R4 (04h) Audio interface 15:14 DACDATA_PUL L [1:0] 00 DACDAT pull-up / pull-down Enable 00 = no pull-up or pull-down 01 = pull-down 10 = pull-up 11 = reserved 13:12 FRAME_PULL [1:0] 00 LRCLK pull-up / pull-down Enable 00 = no pull-up or pull-down 01 = pull-down 10 = pull-up 11 = reserved 11:10 BCLK_PULL [1:0] 00 BCLK pull-up / pull-down Enable 00 = no pull-up or pull-down 01 = pull-down 10 = pull-up 11 = reserved Table 50 Pull-Up and Pull-Down Control CLOCKING AND SAMPLE RATES The internal clocks for the CODEC and Digital Audio Interface are derived from a common internal clock source, SYSCLK. This clock can either be derived directly from MCLK, or may be generated using the Frequency Locked Loop (FLL) using MCLK as a reference. All commonly-used audio sample rates can be derived directly from typical MCLK frequencies; the FLL provides additional flexibility for a wider range of MCLK frequencies. The WM8944B supports a wide range of standard audio sample rates from 8kHz to 48kHz. When the ADC and DAC are both enabled, they operate at the same sample rate, fs. Other functions such as the Interrupts and GPIO input de-bounce are clocked using a free-running oscillator. The control registers associated with Clocking and Sample Rates are described in Table 51. The overall clocking scheme for the WM8944B is illustrated in Figure 31. |
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