WM8944BECSSLASHR datasheet(26/165 Pages) CIRRUS

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WM8944B

Rev 4.3

DIGITAL MICROPHONE INTERFACE

The WM8944B supports a stereo digital microphone interface, using the IN1/DMICDAT input pin for

data and a GPIO pin for the data clock. The analogue signal path from the IN1/DMICDAT pin must be

disabled when using the digital microphone interface; this is achieved by disabling the input PGA, (ie.

INPGA_ENA = 0).

Note that, although the WM8944B is largely a mono device, it supports a stereo signal path from the

digital microphone interface to the digital audio interface. DSP processing, including 3D stereo

enhancement, can be enabled on this signal path -

see the “DSP Core” section.

The Digital Microphone Input, DMICDAT, is provided on the IN1/DMICDAT pin. The associated clock,

DMICCLK, is provided on a GPIO pin.

The Digital Microphone Input is selected as input by setting the DMIC_ENA bit. When the Digital

Microphone Input is selected, the ADC input is deselected.

The digital microphone interface configuration is illustrated in Figure 9.

Note that the digital microphone may be powered from MICBIAS or from LDOVOUT; care must be

taken to ensure that the respective digital logic levels of the microphone are compatible with the digital

input thresholds of the WM8944B. The digital input thresholds are referenced to DBVDD, as defined in

“Electrical Characteristics”.

DRC

Input PGA

MICBIAS

DMIC

DMICDAT

DMICCLK

MICBIAS

Digital Audio

Interface

(ADCDAT)

ADC

Volume

HPF

DMIC_ENA

GPIOn

IN1/

DMICDAT

Decimation

ADC

DMIC

interface

GPIO

ADCL_ENA

ADCR_ENA

SR[3:0]

INPGA_ENA=0

Figure 9 Digital Microphone Interface

When any GPIO pin is configured as DMICCLK output, the WM8944B outputs a clock which supports

Digital Mic operation at the ADC sampling rate. The ADC and Record Path filters must be enabled

and the ADC sampling rate must be set in order to ensure correct operation of all DSP functions

associated with the digital microphone. Volume control for the Digital Microphone Interface signals is

provided using the ADC Volume Control.

The WM8944B supports stereo digital microphone operation. The ADCL_ENA register enables the

Left channel; the ADCR_ENA register enables the Right channel. Note that only the digital blocks are

enabled by the ADCR_ENA register.

See “Analogue-to-Digital Converter (ADC)” for details of the ADC Enable and volume control

functions. See “General Purpose Input/Output” for details of configuring the DMICCLK output. See

“Clocking and Sample Rates” for the details of the sample rate control.

When the DMIC_ENA bit is set, then the IN1 pin is used as the digital microphone input DMICDAT.

Up to two microphones can share this pin; the two microphones are interleaved as illustrated in Figure

10.

The digital microphone interface requires that MIC1 (Left Channel) transmits a data bit each time that

DMICCLK is high, and MIC2 (Right Channel) transmits when DMICCLK is low. The WM8944B

samples the digital microphone data in the middle of each DMICCLK clock phase. Each microphone

must tri-state its data output when the other microphone is transmitting.

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