WM8944BECSSLASHR datasheet(21/165 Pages) CIRRUS

21 / 165 page

WM8944B

Rev 4.3

DEVICE DESCRIPTION

INTRODUCTION

The WM8944B is a highly integrated low power hi-fi CODEC designed for portable devices such as

digital still cameras and multimedia phones. Flexible analogue interfaces and powerful digital signal

processing (DSP) in a 2.41 x 2.41mm footprint make it ideal for small portable devices.

The WM8944B supports up to 2 analogue audio inputs. One single-ended or pseudo differential

microphone / line input may be selected as the ADC input source. The analogue inputs can also be

configured as inputs to the output mixers, either as two single ended inputs or as a differential pair. An

integrated bias reference is provided to power standard electret microphones. A stereo digital

microphone interface is also supported, with direct input to the DSP core.

The hi-fi ADC and DAC operate at sample rates from 8kHz up to 48kHz. A high pass filter is available

in the ADC path for removing DC offsets and suppressing low frequency noise such as mechanical

vibration and wind noise. A digital tone (‘beep’) generator allows audio tones to be injected into the

DAC output path.

The WM8944B provides a powerful DSP capability for configurable filtering and processing of the

digital audio path. The DSP provides low-pass / high-pass filtering, notch filters, 5-band EQ, dynamic

range control (DRC) and a programmable DF1 digital filter. The tuned notch filters allow narrow

frequency bands to be attenuated, to provide filtering of motor noise or other unwanted sounds; the 5-

band EQ allows the signal to be adjusted for user-preferences. The dynamic range control provides a

range of compression, limiting and noise gate functions to support optimum configuration for recording

or playback modes. The DF1 filter allows user-specified filters to be implemented in the digital signal

chain. 3D stereo enhancement is provided; this may be used on the stereo digital microphone input

path.

The ReTune

™ feature is a highly-configurable DSP algorithm which can be tailored to cancel or

compensate for imperfect characteristics of the housing, loudspeaker or microphone components in

the target application. The ReTune algorithm coefficients and register contents are calculated using

Cirrus Logic’s WISCE™ software; lab bench tests and audio reference measurements must be

performed in order to determine the optimum settings.

The digital signal routing between the ADC, DAC and I2S digital audio interface can be configured in

different ways according to the application requirements. The DSP functions may be applied to the

ADC record path, the DAC playback path, or split between the two paths (refer to the DSP

Configuration Modes section).

Two analogue output mixers are provided, connected to 3 analogue output pins. A mono line output

and mono BTL speaker may be connected to these outputs.

The WM8944B incorporates an LDO regulator for compatibility with a wide range of supply rails; the

internal LDO can also reduce any interference resulting from a noisy supply rail. The LDO regulator

can also be used to provide a regulated supply voltage to other circuits.

I2C or SPI control interface modes for read/write access to the register map. A single external clock

provides timing reference for all the digital functions; an integrated Frequency Locked Loop (FLL) also

provides flexibility to perform frequency conversions and to remove noise/jitter from the external clock.

The FLL can be configured for reduced power consumption, or for different filtering requirements of

the reference source.

Additional functions include a current-mode video buffer providing excellent video signal reproduction

at low operating voltages. Up to 2 GPIO pins may be configured for miscellaneous input/output, or for

status indications from the temperature monitoring functions.

WM8944BECS/R 数据表(PDF) 21 Page - Cirrus Logic

WM8944BECS/R 数据表(HTML) 21 Page - Cirrus Logic

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载