WM8944BECSSLASHR datasheet(84/165 Pages) CIRRUS

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WM8944B

Rev 4.3

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

4:3

VB_DISOFF

[1:0]

111

Video buffer DC offset control

000 = Reserved

001 = 40mV offset

010 = Reserved

011 = 20mV offset

100 = Reserved

101 = Reserved

110 = Reserved

111 = 0mV offset

Note - the specified offset applies to

the 0dB gain setting (VB_GAIN=0).

When 6dB gain is selected, the DC

offset is doubled.

VB_PD

Video buffer pull-down

0 = pull-down disabled

1 = pull-down enabled

VB_CLAMP

Enable the clamp between the

video input and ground

0 = no clamp

1 = Video buffer input is clamped to

ground

Table 57 Video Buffer Control

The video buffer circuit is illustrated in Figure 33.

LDOVDD

VBREF

VIDEO BUFFER

VBIN

VBOUT

TV in

6dB / 12dB (unloaded)

0dB / 6dB (fully loaded)

LPF

clamp

RREF

RSOURCE

RLOAD

Figure 33 Video Buffer Block Diagram

The video buffer requires two external resistor components, as illustrated in Figure 33. For best

performance, the resistor RSOURCE should be matched (equal) to the load impedance RLOAD.

The resistance RREF is a function of the circuit gain and a function of the parallel combination of

RSOURCE and RLOAD. When VB_GAIN = 0 (0dB gain), the current gain of the video buffer is 5, as

described by the equation IVBOUT = 5 x IVBREF.

The resistor RREF should be set equal to 5 x (RSOURCE // RLOAD), where (RSOURCE // RLOAD) is the effective

resistance of the parallel combination of RSOURCE and RLOAD. (Note that the required resistance RREF is

the same for both settings of VB_GAIN.)

In a typical application, RLOAD = 75, RSOURCE = 75, RREF = 187.

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