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WM8944BECS/R 数据表(PDF) 69 Page - Cirrus Logic

部件名 WM8944BECS/R
功能描述  Mono Low-Power CODEC with Video Buffer
PDF  165 Pages
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制造商  CIRRUS [Cirrus Logic]
网页  http://www.cirrus.com
标志 CIRRUS - Cirrus Logic

WM8944BECS/R 数据表(HTML) 69 Page - Cirrus Logic

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WM8944B
Rev 4.3
69
In I2S mode, the MSB is available on the second rising edge of BCLK following a LRCLK transition.
The other bits up to the LSB are then transmitted in order. Depending on word length, BCLK
frequency and sample rate, there may be unused BCLK cycles between the LSB of one sample and
the MSB of the next.
n
n-1
n-2
3
2
1
n
n-1
n-2
3
2
1
LEFT CHANNEL
RIGHT CHANNEL
MSB
LSB
Input Word Length (WL)
1/fs
LRCLK
BCLK
DACDAT/
ADCDAT
1 BCLK
1 BCLK
Figure 22 I2S Justified Audio Interface (assuming n-bit word length)
In DSP/PCM mode, the left channel MSB is available on either the 1st (mode B) or 2nd (mode A) rising
edge of BCLK (selected by LRCLK_INV) following a rising edge of LRCLK. Right channel data
immediately follows left channel data. Depending on word length, BCLK frequency and sample rate,
there may be unused BCLK cycles between the LSB of the right channel data and the next sample.
In device master mode, the LRCLK output resembles the frame pulse shown in Figure 23 and Figure
24. In device slave mode, Figure 25 and Figure 26, it is possible to use any length of frame pulse less
than 1/fs, providing the falling edge of the frame pulse occurs greater than one BCLK period before
the rising edge of the next frame pulse.
n
n-1
n-2
3
2
1
n
n-1
n-2
3
2
1
LEFT CHANNEL
RIGHT CHANNEL
MSB
LSB
Input Word Length (WL)
1/fs
LRCLK
BCLK
DACDAT/
ADCDAT
1 BCLK
1/2fs
Figure 23 DSP/PCM Mode Audio Interface (mode A, LRCLK_INV=0, Master)
n
n-1
n-2
3
2
1
n
n-1
n-2
3
2
1
LEFT CHANNEL
RIGHT CHANNEL
MSB
LSB
Input Word Length (WL)
1/fs
LRCLK
BCLK
DACDAT/
ADCDAT
1/2fs
Figure 24 DSP/PCM Mode Audio Interface (mode B, LRCLK_INV=1, Master)



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