WM8944BECSSLASHR datasheet(17/165 Pages) CIRRUS

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WM8944B

Rev 4.3

SIGNAL TIMING REQUIREMENTS

SYSTEM CLOCK TIMING

MCLK

tMCLKL

tMCLKH

tMCLKY

Figure 2 Master Clock Timing

Test Conditions

DCVDD = 1.8V, DBVDD = LDOVDD = SPKVDD = 3.3V, LDOVOUT = 3.0V, GND = 0V, TA = +25

oC.

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNIT

Master Clock Timing

MCLK cycle time

TMCLKY

0.037

s

MCLK duty cycle

(= TMCLKH : TMCLKL)

60:40

40:60

AUDIO INTERFACE TIMING

MASTER MODE

BCLK (Output)

ADCDAT

LRCLK (Output)

DACDAT

DDA

DHT

DST

Figure 3 Audio Interface Timing - Master Mode

Test Conditions

DCVDD = 1.8V, DBVDD = LDOVDD = SPKVDD = 3.3V, LDOVOUT = 3.0V, GND = 0V,

TA = +25

oC, 1kHz signal, fs = 48kHz, PGA gain = 0dB, 24-bit audio data unless otherwise stated.

PARAMETER

SYMBOL

MIN

TYP

MAX

UNIT

Audio Interface Timing - Master Mode

LRCLK propagation delay from BCLK falling edge

tDL

ADCDAT propagation delay from BCLK falling edge

tDDA

DACDAT setup time to BCLK rising edge

tDST

DACDAT hold time from BCLK rising edge

tDHT

WM8944BECS/R 数据表(PDF) 17 Page - Cirrus Logic

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