WM8944BECSSLASHR datasheet(87/165 Pages) CIRRUS

87 / 165 page

WM8944B

Rev 4.3

GENERAL PURPOSE INPUT/OUTPUT

The WM8944B provides two multi-function pins which can be configured to provide a number of

different functions. These are digital input/output pins on the DBVDD power domain. The GPIO pins

are:



¯¯ /GPIO1



CIFMODE/GPIO2

Note that the GPIO pins are shared with Control Interface functions. The pins available for GPIO

function depend on the selected Control Interface mode, as described in Table 60.

CONTROL INTERFACE MODE

GPIO PIN AVAILABILITY

2-wire (I2C)

GPIO1

GPIO2

3-wire (SPI)

GPIO2

Table 60 GPIO Pin Availability

Note that CIFMODE/GPIO2 pin selects between I2C and SPI Control Interface modes

(see “Control

Interface”). To enable GPIO functions on GPIO2, the MODE_GPIO register bit must be set in order to

disconnect this pin from the Control Interface circuit. Setting the MODE_GPIO register bit causes the

Control Interface mode selection to be latched; it will remain latched until a Software Reset or Power

On Reset occurs.

The register fields that control the GPIO pins are described in Table 61.

For each GPIO, the selected function is determined by the GPn_FN field, where n identifies the GPIO

pin (1 or 2). The pin direction, set by GPn_DIR, must be set according to function selected by

GPn_SEL.

When a pin is configured as a GPIO output, its level can be set to logic 0 or logic 1 using the

GPn_LVL field. When a pin is configured as a GPIO input, the logic level can be read from the

respective GPn_LVL bit. The GPIO output is inverted with respect to the GPn_LVL register when the

polarity bit GPn_POL is set; the equivalent is true of GPIO inputs also.

Internal pull-up and pull-down resistors may be enabled using the GPn_PULL fields; this allows

greater flexibility to interface with different signals from other devices.

Each of the GPIO pins is an input to the Interrupt control circuit and can be used to trigger an Interrupt

event. This may be configured as level-triggered or edge-triggered using the GPn_FN registers. Edge

detect raises an interrupt when the GPIO status changes; level detect asserts the interrupt for as long

as the GPIO status is asserted. See “Interrupts”.

An edge-triggered GPIO can be configured to trigger on a single edge or on both edges of the input

signal; this is selected using the GPn_INT_MODE registers. A level-triggered or single-edge-triggered

input may be configured using the GPn_POL registers to respond to a high level/edge (when

GPn_POL = 0) or a low level/edge (when GPn_POL = 1).

The GPIO control fields are defined in Table 61.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R11 (0Bh)

GPIO Config

MODE_GPIO

CIFMODE/GPIO2 pin configuration

0 = Pin configured as CIFMODE

1 = Pin configured as GPIO2

Note - when this bit is set to 1, it is

latched and cannot be reset until

Power-Off or Software Reset.

R13 (0Dh)

GPIO1

Control

GP1_DIR

GPIO1 Pin Direction

0 = Output

1 = Input

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