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数据搜索系统，热门电子元器件搜索 |
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数据搜索系统，热门电子元器件搜索 |
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WM8944BECS/R 数据表(PDF) 20 Page - Cirrus Logic |
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WM8944BECS/R 数据表(HTML) 20 Page - Cirrus Logic |
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20 / 165 page  WM8944B 20 Rev 4.3 CS (input) SCLK (input) SDA (input) tCSU tCHO tSCH tSCL tSCY tDHO tDSU Figure 6 Control Interface Timing - 3-wire (SPI) Control Mode (Write Cycle) Note: The data is latched on the 32nd falling edge of SCLK after 32 bits have been clocked into the device. SCLK (input) SDA (output) tDL CS (input) Figure 7 Control Interface Timing - 3-wire (SPI) Control Mode (Read Cycle) Test Conditions DCVDD = 1.8V, DBVDD = LDOVDD = SPKVDD = 3.3V, LDOVOUT = 3.0V, GND = 0V, TA = +25 oC, 1kHz signal, fs = 48kHz, PGA gain = 0dB, 24-bit audio data unless otherwise stated. PARAMETER SYMBOL MIN TYP MAX UNIT CS ¯¯ falling edge to SCLK rising edge tCSU 40 ns SCLK falling edge to CS ¯¯ rising edge tCHO 10 ns SCLK pulse cycle time tSCY 200 ns SCLK pulse width low tSCL 80 ns SCLK pulse width high tSCH 80 ns SDA to SCLK set-up time tDSU 40 ns SDA to SCLK hold time tDHO 10 ns Pulse width of spikes that will be suppressed tps 0 5 ns SCLK falling edge to SDA output transition tDL 40 ns |
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