WM8944BECSSLASHR datasheet(81/165 Pages) CIRRUS

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WM8944B

Rev 4.3

EXAMPLE FLL CALCULATION

To generate 24.576MHz output (FOUT) from a 12.000MHz reference clock (FREF):



Set FLL_CLK_REF_DIV in order to generate FREF <=13.5MHz:

FLL_CLK_REF_DIV = 00 (divide by 1)



Set FLL_CTRL_RATE to the recommended setting:

FLL_CTRL_RATE = 000 (divide by 1)



Sett FLL_GAIN to the recommended setting:

FLL_GAIN = 0000 (multiply by 1)



Set FLL_OUTDIV for the required output frequency as shown in Table 53:-

FOUT = 24.576MHz, therefore FLL_OUTDIV = 1h (divide by 4)



Set FLL_FRATIO for the given reference frequency as shown in Table 54:

FREF = 12MHz, therefore FLL_FRATIO = 0h (divide by 1)



Calculate FVCO as given by FVCO = FOUT x FLL_OUTDIV:-

FVCO = 24.576 x 4 = 98.304MHz



Calculate N.K as given by N.K = FVCO / (FLL_FRATIO x FREF):

N.K = 98.304 / (1 x 12) = 8.192



Determine FLL_N and FLL_K from the integer and fractional portions of N.K:-

FLL_N is 8(dec) = 008(hex). FLL_K is 0.192 (dec) = 3127(hex).



Confirm that N.K is a fractional quantity and set FLL_FRAC:

N.K is fractional. Set FLL_FRAC = 1.

Note that, if N.K is an integer, then an alternative value of FLL_FRATIO may be selected in

order to produce a fractional value of N.K.

WM8944BECS/R 数据表(PDF) 81 Page - Cirrus Logic