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WM8944BECS/R 数据表(PDF) 93 Page - Cirrus Logic

部件名 WM8944BECS/R
功能描述  Mono Low-Power CODEC with Video Buffer
PDF  165 Pages
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制造商  CIRRUS [Cirrus Logic]
网页  http://www.cirrus.com
标志 CIRRUS - Cirrus Logic

WM8944BECS/R 数据表(HTML) 93 Page - Cirrus Logic

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WM8944B
Rev 4.3
93
device ID
B9
B8
D1
B15
data bits B15
– B8
ACK
R/W
(Read)
B1
B0
B7
data bits B15
– B8
ACK
STOP
ACK
A9
D7
D1
A15
SDA
SCLK
device ID
device ID
A8
D7
Note: The SDA pin is driven by both the master and slave devices in turn to transfer device address, register address, data and ACK responses
R/W
register address A15
– A8
START
(Write)
ACK
ACK
Rpt
START
A1
A7
A0
register address A7
– A0
Figure 35 Control Interface 2-wire (I2C) Register Read
The Control Interface also supports other register operations, as listed above. The interface protocol
for these operations is summarised below. The terminology used in the following figures is detailed in
Table 66.
Note that, for multiple write and multiple read operations, the auto-increment option must be enabled.
This feature is enabled by default, as noted in Table 65.
TERMINOLOGY
DESCRIPTION
S
Start Condition
Sr
Repeated start
A
Acknowledge (SDA Low)
A
¯¯
Not Acknowledge (SDA High)
P
Stop Condition
R/W
¯¯
ReadNotWrite
0 = Write
1 = Read
[White field]
Data flow from bus master to WM8944B
[Grey field]
Data flow from WM8944B to bus master
Table 66 Control Interface Terminology
Device ID
S
A
MSByte Address
(0)
A
MSByte Data
A
LSByte Data
A
P
8 bit Device ID
8 bits
8 bits
8 bits
LSByte Address
A
8 bits
RW
Figure 36 Single Register Write to Specified Address
Device ID
Sr
A
P
MSByte Data
(1)
LSByte Data
A
Device ID
S
A
MSByte Address
(0)
A
A
A
LSByte Address
RW
RW
Figure 37 Single Register Read from Specified Address



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