WM8944BECSSLASHR datasheet(89/165 Pages) CIRRUS

89 / 165 page

WM8944B

Rev 4.3

The GPIO input functions may be used to detect headphone jack insertion or a button press. These

signals may be used as inputs to the Interrupt Controller, via the integrated de-bounce circuit.

GPn_FN

DESCRIPTION

COMMENTS

0000

Logic level input

External logic level is read from GPn_LVL.

Associated interrupt (when enabled) is level-triggered.

0001

Edge detection input

External logic level is read from GPn_LVL.

Associated interrupt (when enabled) is edge

triggered. Note that TOCLK_ENA must be set.

0010

CLKOUT output

Output clock frequency is set by CLKOUT_DIV.

0011

Interrupt (IRQ) output

Hardware output of all unmasked Interrupts.

0100

Reserved

0101

Reserved

0110

Reserved

0111

Temperature flag output

Indicates the temperature sensor output. This is a

hardware output of the TEMP_STS bit (assuming

GPn_POL = 0).

0 = Normal

1 = Overtemperature

1000

Reserved

1001

DMICCLK output

Output clock for digital microphone interface

1010

Logic level output

Pin logic level is set by GPn_LVL.

1011

LDO_UV output

Indicates the LDO undervoltage status. This is a

hardware output of the LDO_UV_STS bit (assuming

GPn_POL = 0).

0 = Normal

1 = LDO undervoltage

1100

Reserved

1101

Reserved

1110

Reserved

1111

Reserved

Table 62 GPIO Function Select

INTERRUPTS

The Interrupt Controller has multiple inputs. These include the GPIO input pins, Temperature sensor

and the LDO Regulator. Any combination of these inputs can be used to trigger an Interrupt (IRQ)

event.

There is an Interrupt Status field associated with each of the IRQ inputs. These are listed within the

System Interrupts Register (R16), as described in Table 63. The status of the IRQ inputs can be read

at any time from this register or else in response to the Interrupt (IRQ) output being signalled via a

GPIO pin.

Individual mask bits can select or deselect different functions from the Interrupt controller. These are

listed within the System Interrupts Mask Register (R19), as described in Table 63. Note that the status

fields remain valid, even when masked, but the masked bits will not cause the Interrupt (IRQ) output

to be asserted.

The Interrupt (IRQ) output represents the logical ‘OR’ of all the unmasked IRQ inputs. The bits within

the System Interrupts Register (R16) are latching fields and, once they are set, they are not reset until

the System Interrupts Register is read. Accordingly, the Interrupt (IRQ) output is not reset until the

System Interrupts Register has been read. Note that, if the condition that caused the IRQ input to be

asserted is still valid, then the Interrupt (IRQ) output will remain set even after the System Interrupts

When GPIO input is used to trigger an Interrupt event, polarity can be set using the GPn_POL bits as

described in Table 61. This allows the IRQ event to be used to indicate a rising or a falling edge of the

external logic signal. If desired, the GPn_INT_MODE bits can be used to select an Interrupt event on

both the rising and falling edges.

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