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WM8944BECS/R 数据表(PDF) 66 Page - Cirrus Logic

部件名 WM8944BECS/R
功能描述  Mono Low-Power CODEC with Video Buffer
PDF  165 Pages
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制造商  CIRRUS [Cirrus Logic]
网页  http://www.cirrus.com
标志 CIRRUS - Cirrus Logic

WM8944BECS/R 数据表(HTML) 66 Page - Cirrus Logic

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WM8944B
66
Rev 4.3
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R42 (2Ah)
Output ctrl
7
SPKN_DISCH
0
Discharges SPKOUTN output via
approx 550 ohm resistor
0 = Not active
1 = Actively discharging SPKOUTN
6
SPKP_DISCH
0
Discharges SPKOUTP output via
approx 550 ohm resistor
0 = Not active
1 = Actively discharging SPKOUTP
4
LINE_DISCH
0
Discharges LINEOUT output via
approx 550 ohm resistor
0 = Not active
1 = Actively discharging LINEOUT
Table 43 Output Discharge Control
DIGITAL AUDIO INTERFACE
The digital audio interface is used for inputting DAC data into the WM8944B and outputting ADC data
from it. It uses four pins:
ADCDAT - ADC / Digital Microphone data output
DACDAT - DAC data input
LRCLK - DAC and ADC data alignment clock
BCLK - Bit clock, for synchronisation
MASTER AND SLAVE MODE OPERATION
The digital audio interface can be configured as a Master or a Slave interface, using the MSTR
register bit. The two modes are illustrated in Figure 19 and Figure 20.
WM8944B
ADCDAT
LRCLK
DACDAT
BCLK
Processor
WM8944B
Processor
ADCDAT
LRCLK
DACDAT
BCLK
Figure 19 Master Mode
Figure 20 Slave Mode
In Master mode, LRCLK and BCLK are configured as outputs, and the WM8944B controls the timing
of the data transfer on the ADCDAT and DACDAT pins.
In Master mode, the LRCLK frequency is determined automatically according to the sample rate (see
“Clocking and Sample Rates”). The BCLK frequency is set by the BCLK_DIV register. BCLK_DIV
must be set to an appropriate value to ensure that there are sufficient BCLK cycles to transfer the
complete data words from the ADCs and to the DACs.
In Slave mode, LRCLK and BCLK are configured as inputs, and the data timing is controlled by an
external master.



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